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Features
* High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture
- 130 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers + Peripheral Control Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-chip 2-cycle Multiplier Non-volatile Program and Data Memories - 64K Bytes of In-System Reprogrammable Flash Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 2K Bytes EEPROM Endurance: 100,000 Write/Erase Cycles - 4K Bytes Internal SRAM - Up to 64K Bytes Optional External Memory Space - Programming Lock for Software Security - SPI Interface for In-System Programming JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Two 8-bit PWM Channels - 6 PWM Channels with Programmable Resolution from 1 to 16 Bits - 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels 2 Differential Channels with Programmable Gain (1x, 10x, 200x) - Byte-oriented Two-wire Serial Interface - Dual Programmable Serial USARTs - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby - Software Selectable Clock Frequency - ATmega103 Compatibility Mode Selected by a Fuse - Global Pull-up Disable I/O and Packages - 53 Programmable I/O Lines - 64-lead TQFP and 64-pad QFN/MLF Operating Voltages - 2.7 - 5.5V for ATmega64L - 4.5 - 5.5V for ATmega64 Speed Grades - 0 - 8 MHz for ATmega64L - 0 - 16 MHz for ATmega64
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8-bit Microcontroller with 64K Bytes In-System Programmable Flash ATmega64 ATmega64L
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Pin Configuration
Figure 1. Pinout ATmega64
TQFP/MLF
PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6
Note:
The bottom pad under the QFN/MLF package should be soldered to ground.
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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(OC2/OC1C) PB7 TOSC2/PG3 TOSC1/PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2(ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10 PC1 (A9) PC0 (A8) PG1(RD) PG0(WR)
ATmega64(L)
Overview
The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
PF0 - PF7 PA0 - PA7 PC0 - PC7
VCC GND PORTF DRIVERS AVCC DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS PORTA DRIVERS PORTC DRIVERS
XTAL1 AREF ADC INTERNAL OSCILLATOR XTAL2 OSCILLATOR JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER CALIB. OSC
OSCILLATOR
ON-CHIP DEBUG
PROGRAM FLASH
SRAM
MCU CONTROL REGISTER
TIMING AND CONTROL RESET
BOUNDARYSCAN
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTERS
PEN
PROGRAMMING LOGIC
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
ALU
EEPROM
STATUS REGISTER
USART0
SPI
USART1
2-WIRE SERIAL INTERFACE
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
DATA REG. DATA DIR. PORTG REG. PORTG
+ -
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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The ATmega64 provides the following features: 64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run. The device is manufactured using Atmel's high-density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega64 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.
ATmega103 and ATmega64 Compatibility
The ATmega64 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega64. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF (i.e., in the ATmega103 internal RAM space). These location can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed. The ATmega64 is 100% pin compatible with ATmega103, and can replace the ATmega103 on current printed circuit boards. The application notes "Replacing ATmega103 by ATmega128" and "Migration between ATmega64 and ATmega128" describes what the user should be aware of replacing the ATmega103 by an ATmega128 or ATmega64.
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ATmega103 Compatibility Mode By programming the M103C Fuse, the ATmega64 will be compatible with the ATmega103 regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new features in ATmega64 are not available in this compatibility mode, these features are listed below: * * * * * * * * One USART instead of two, asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. One 16 bits Timer/Counter with two compare registers instead of two 16 bits Timer/Counters with three compare registers. Two-wire serial interface is not supported. Port G serves alternate functions only (not a general I/O port). Port F serves as digital input only in addition to analog input to the ADC. Boot Loader capabilities is not supported. It is not possible to adjust the frequency of the internal calibrated RC Oscillator. The External Memory Interface can not release any Address pins for general I/O, neither configure different wait states to different External Memory Address sections. Only EXTRF and PORF exist in the MCUCSR Register. No timed sequence is required for Watchdog Timeout change. Only low-level external interrupts can be used on four of the eight External Interrupt sources. Port C is output only. USART has no FIFO buffer, so Data OverRun comes earlier. The user must have set unused I/O bits to 0 in ATmega103 programs.
* * * * * *
Pin Descriptions
VCC GND Port A (PA7..PA0) Digital supply voltage. Ground. Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega64 as listed on page 73. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega64 as listed on page 74.
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Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega64 as listed on page 77. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega64 as listed on page 78.
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega64 as listed on page 81.
Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input port only.
Port G (PG4..PG0)
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are Oscillator pins.
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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page 52. Shorter pulses are not guaranteed to generate a reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the inverting Oscillator amplifier. AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. AREF is the analog reference pin for the A/D Converter. This is a programming enable pin for the SPI Serial Programming mode. By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation.
XTAL1 XTAL2 AVCC
AREF PEN
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Resources
A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.
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About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
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AVR CPU Core
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 3. Block Diagram of the AVR MCU Architecture
Architectural Overview
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle.
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses which can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega64 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description.
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Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
SREG - AVR Status Register
The AVR Status Register - SREG - is defined as:
Bit 0x3F (0x5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared in software with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information.
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* Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information.
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * * * * One 8-bit output operand and one 8-bit result input. Two 8-bit output operands and one 8-bit result input. Two 8-bit output operands and one 16-bit result input. One 16-bit output operand and one 16-bit result input.
Figure 4 shows the structure of the 32 general purpose working registers in the CPU. Figure 4. AVR CPU General Purpose Working Registers
7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
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X-, Y-, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5. The X-, Y-, and Z-Registers
15 X - register 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0
15 Y - register 7 R29 (0x1D)
YH 0 7 R28 (0x1C)
YL
0 0
15 Z - register 7 R31 (0x1F)
ZH 0 7 R30 (0x1E)
ZL
0 0
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details).
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. If software reads the Program Counter from the Stack after a call or an interrupt, unused bits (bit 15) should be masked out. The Stack Pointer points to the data SRAM Stack area where the subroutine and interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
Bit 0x3E (0x5E) 0x3D (0x5D) 15 SP15 SP7 7 Read/Write R/W R/W Initial Value 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL
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Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7. Single Cycle ALU Operation
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section "Memory Programming" on page 291 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 61. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to "Interrupts" on page 61 for more information. The Reset Vector can also be 15
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moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see "Boot Loader Support - Read-While-Write Self-programming" on page 278. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example
in cli r16, SREG ; store SREG value ; start EEPROM write ; restore SREG value (I-bit) ; disable interrupts during timed sequence
sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16
C Code Example
char cSREG; cSREG = SREG; _CLI(); EECR |= (1<16
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When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example
sei ; set global interrupt enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s)
C Code Example
_SEI(); /* set global interrupt enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
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AVR Memories
This section describes the different memories in the ATmega64. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega64 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. The ATmega64 contains 64K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega64 Program Counter (PC) is 15 bits wide, thus addressing the 32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in "Boot Loader Support - ReadWhile-Write Self-programming" on page 278. "Memory Programming" on page 291 contains a detailed description on Flash programming in SPI, JTAG, or Parallel Programming mode. Constant tables can be allocated within the entire program memory address space (see the LPM - Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in "Instruction Execution Timing" on page 15. Figure 8. Program Memory Map
In-System Reprogrammable Flash Program Memory
$0000
Application Flash Section
Boot Flash Section $7FFF
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SRAM Data Memory
The ATmega64 supports two different configurations for the SRAM data memory as listed in Table 1. Table 1. Memory Configurations
Configuration Normal mode ATmega103 compatibility mode Internal SRAM Data Memory 4096 4000 External SRAM Data Memory up to 64K up to 64K
Figure 9 on page 20 shows how the ATmega64 SRAM Memory is organized. The ATmega64 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the ATmega64 is in the ATmega103 compatibility mode. The first 4,352 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4,096 locations address the internal data SRAM. In ATmega103 compatibility mode, the first 4,096 data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, and the next 4,000 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega64. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register File, I/O, Extended I/O and internal SRAM occupy the lowest 4,352 bytes in Normal mode, and the lowest 4,096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so when using 64KB (65,536 bytes) of External memory, 61,184 Bytes of External memory are available in Normal mode, and 61,440 Bytes in ATmega103 compatibility mode. See "External Memory Interface" on page 27 for details on how to take advantage of the external memory map. When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR Register. Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the 2-byte Program Counter is pushed and popped, and external memory access does not take advantage of the internal pipeline memory access. When external SRAM interface is used with wait state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait states respectively. Interrupt, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the AVR Instruction Set manual for one, two, and three waitstates.
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The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 extended I/O Registers, and the 4,096 bytes of internal data SRAM in the ATmega64 are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page 13. Figure 9. Data Memory Map
Memory Configuration A
Data Memory
32 Registers 64 I/O Registers 160 Ext I/O Reg. Internal SRAM (4096 x 8) $10FF $1100 External SRAM (0 - 64K x 8) $0000 - $001F $0020 - $005F $0060 - $00FF $0100
Memory Configuration B
Data Memory
32 Registers 64 I/O Registers Internal SRAM (4000 x 8) $0FFF $1000 $0000 - $001F $0020 - $005F $0060
External SRAM (0 - 64K x 8)
$FFFF
$FFFF
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Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10. On-chip Data SRAM Access Cycles
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address Valid
Memory Access Instruction
Next Instruction
EEPROM Data Memory
The ATmega64 contains 2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. "Memory Programming" on page 291 contains a detailed description on EEPROM programming in SPI, JTAG, or Parallel Programming mode.
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 2 on page 24. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Powerup/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See "Preventing EEPROM Corruption" on page 26. for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
Read
Write
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EEARH and EEARL - EEPROM Address Register
Bit 0x1F (0x3F) 0x1E (0x3E)
15 - EEAR7 7
14 - EEAR6 6 R R/W 0 X
13 - EEAR5 5 R R/W 0 X
12 - EEAR4 4 R R/W 0 X
11 - EEAR3 3 R R/W 0 X
10 EEAR10 EEAR2 2 R/W R/W X X
9 EEAR9 EEAR1 1 R/W R/W X X
8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
Read/Write
R R/W
Initial Value
0 X
* Bits 15..11 - Res: Reserved Bits These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices. * Bits 10..0 - EEAR10..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 2,048. The Initial Value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. EEDR - EEPROM Data Register
Bit 0x1D (0x3D) Read/Write Initial Value
7 MSB R/W 0
6
5
4
3
2
1
0 LSB EEDR
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bits 7..0 - EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. EECR - EEPROM Control Register
Bit 0x1C (0x3C) Read/Write Initial Value
7 - R 0
6 - R 0
5 - R 0
4 - R 0
3 EERIE R/W 0
2 EEMWE R/W 0
1 EEWE R/W X
0 EERE R/W 0 EECR
* Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATmega64 and will always read as zero. * Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared.
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* Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. * Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See "Boot Loader Support - Read-While-Write Self-programming" on page 278 for details about Boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during the four last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical programming time for EEPROM access from the CPU.
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Table 2. EEPROM Programming Time(1)
Symbol EEPROM write (from CPU) Note: Number of Calibrated RC Oscillator Cycles 8448 Typ Programming Time 8.4 ms
1. Uses 1 MHz clock, independent of CKSEL Fuse settings.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example
EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out out out sbi sbi ret EEARH, r18 EEARL, r17 EEDR,r16 EECR,EEMWE EECR,EEWE
; Write data (r16) to data register ; Write logical one to EEMWE ; Start eeprom write by setting EEWE
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<24
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example
EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out out sbi in ret EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR
; Start eeprom read by writing EERE ; Read data from data register
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<EEPROM Write During Powerdown Sleep Mode
When entering Power-down Sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down.
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Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
I/O Memory
The I/O space definition of the ATmega64 is shown in "Register Summary" on page 372. All ATmega64 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega64 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space is replaced with SRAM locations when the ATmega64 is in the ATmega103 compatibility mode. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and peripherals control registers are explained in later sections.
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External Memory Interface
With all the features that the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The main features are: * * * * Overview Four different wait-state settings (Including no wait-state). Independent wait-state setting for different external memory sectors (configurable sector size). The number of bits dedicated to address high byte is selectable. Bus Keepers on data lines to minimize current consumption (optional).
When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available using the dedicated external memory pins (see Figure 1 on page 2, Table 27 on page 73, Table 33 on page 77, and Table 45 on page 85). The memory configuration is shown in Figure 11. Figure 11. External Memory with Sector Select(1)
Memory Configuration A 0x0000 Memory Configuration B 0x0000
Internal Memory
Internal Memory 0x0FFF 0x1000 0x10FF 0x1100
Lower Sector SRW01 SRW00 SRW10 External Memory (0-60K x 8)
SRL[2..0] External Memory (0-60K x 8) Upper Sector
SRW11 SRW10
0xFFFF
0xFFFF
Note:
1. ATmega64 in non ATmega103 compatibility mode: Memory Configuration A is available (Memory Configuration B N/A). ATmega64 in mega103 compatibility mode: Memory Configuration B is available (Memory Configuration A N/A).
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ATmega103 Compatibility
Both External Memory Control Registers, XMCRA and XMCRB, are placed in Extended I/O space. In ATmega103 compatibility mode, these registers are not available, and the features selected by these registers are not available. The device is still ATmega103 compatible, as these features did not exist in ATmega103. The limitations in ATmega103 compatibility mode are: * * * * * Only two wait-state settings are available (SRW1n = 0b00 and SRW1n = 0b01). The number of bits that are assigned to address high byte are fixed. The external memory section cannot be divided into sectors with different wait-state settings. Bus Keeper is not available. RD, WR, and ALE pins are output only (Port G in ATmega64).
Using the External Memory Interface
The interface consists of: * * * * * AD7:0: Multiplexed low-order address bus and data bus. A15:8: High-order address bus (configurable number of bits). ALE: Address latch enable. RD: Read strobe. WR: Write strobe.
The control bits for the External Memory Interface are located in three registers, the MCU Control Register - MCUCR, the External Memory Control Register A - XMCRA, and the External Memory Control Register B - XMCRB. When the XMEM interface is enabled, the XMEM interface will override the setting in the Data Direction Registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section "I/O Ports" on page 66. The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, data, and the control signals on the ports according to Figure 13 (this figure shows the wave forms without wait states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled, also an internal access will cause activity on address-, data- and ALE ports, but the RD and WR strobes will not toggle during internal access. When the external memory interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal latch (typically 74 x 573 or equivalent) which is transparent when G is high. Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at conditions above these frequencies, the typical old style 74HC series latch becomes inadequate. The external memory interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are: * * * D to Q propagation delay (tpd). Data setup time before G low (tsu). Data (address) hold time after G low (th).
The external memory interface is designed to guaranty minimum address hold time after G is asserted low of th = 5 ns (refer to tLAXX_LD/tLLAXX_ST in Table 137 to Table 144 on page 339). The D to Q propagation delay (tpd) must be taken into consideration when calculating the access time requirement of the external component. The data setup time
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before G low (tsu) must not exceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent on the capacitive load). Figure 12. External SRAM Connected to the AVR
D[7:0] AD7:0 ALE D G Q A[7:0]
AVR
A15:8 RD WR
Pull-up and Bus Keeper
SRAM
A[15:8] RD WR
The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port Register to zero before entering sleep. The XMEM interface also provides a Bus Keeper on the AD7:0 lines. The Bus Keeper can be disabled and enabled in software as described in "XMCRB - External Memory Control Register B" on page 34. When enabled, the Bus Keeper will ensure a defined logic level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
Timing
External memory devices have different timing requirements. To meet these requirements, the ATmega64 XMEM interface provides four different wait states as shown in Table 4. It is important to consider the timing specification of the external memory device before selecting the wait-state. The most important parameters are the access time for the external memory compared to the set-up requirement of the ATmega64. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse is asserted low until data must be stable during a read sequence (tLLRL+ tRLRH - tDVRH in Table 137 to Table 144 on page 339). The different wait states are set up in software. As an additional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings. This makes it possible to connect two different memory devices with different timing requirements to the same XMEM interface. For XMEM interface timing details, please refer to Figure 159 to Figure 162, and Table 137 to Table 144. Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guaranteed (varies between devices, temperature, and supply voltage). Consequently the XMEM interface is not suited for synchronous operation.
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Figure 13. External Data Memory Cycles without Wait State(1) (SRWn1 = 0 and SRWn0 =0)
T1 T2 T3 T4
System Clock (CLKCPU )
ALE
A15:8
Prev. addr.
Address
Write
DA7:0
Prev. data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
Prev. data
Address
Data
Read
Read Write
DA7:0 (XMBK = 1)
Prev. data
Address
XXXXX
Data
XXXXXXXX
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).
Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)
T1 T2 T3 T4 T5
System Clock (CLKCPU )
ALE
A15:8
Prev. Addr.
Address
DA7:0
Prev. Data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
Prev. Data
Address
Data
DA7:0 (XMBK = 1)
Prev. Data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).
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Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)
T1 T2 T3 T4 T5 T6
System Clock (CLKCPU )
ALE
A15:8
Prev. Addr.
Address
DA7:0
Prev. Data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
Prev. Data
Address
Data
DA7:0 (XMBK = 1)
Prev. Data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external).
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)
T1
System Clock (CLKCPU )
T2
T3
T4
T5
T6
T7
ALE
A15:8
Prev. Addr.
Address
DA7:0
Prev. Data
Address XX
Data
WR
DA7:0 (XMBK = 0)
Prev. Data
Address
Data
DA7:0 (XMBK = 1)
Prev. Data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external).
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Read
Write
Read
Write
31
XMEM Register Description
MCUCR - MCU Control Register
Bit 0x35 (0x55) Read/Write Initial Value 7 SRE R/W 0 6 SRW10 R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 SM2 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* Bit 7 - SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used. * Bit 6 - SRW10: Wait State Select Bit For a detailed description in non ATmega103 compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14. XMCRA - External Memory Control Register A
Bit (0x6D) Read/Write Initial Value
7 - R 0
6 SRL2 R/W 0
5 SRL1 R/W 0
4 SRL0 R/W 0
3 SRW01 R/W 0
2 SRW00 R/W 0
1 SRW11 R/W 0
0 - R 0 XMCRA
* Bit 7 - Res: Reserved Bit This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for compatibility with future devices. * Bit 6..4 - SRL2, SRL1, SRL0: Wait State Sector Limit It is possible to configure different wait states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits.
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Table 3. Sector Limits with Different Settings of SRL2..0
SRL2 0 0 0 0 1 1 1 1 SRL1 0 0 1 1 0 0 1 1 SRL0 0 1 0 1 0 1 0 1 Sector Limits Lower sector = N/A Upper sector = 0x1100 - 0xFFFF Lower sector = 0x1100 - 0x1FFF Upper sector = 0x2000 - 0xFFFF Lower sector = 0x1100 - 0x3FFF Upper sector = 0x4000 - 0xFFFF Lower sector = 0x1100 - 0x5FFF Upper sector = 0x6000 - 0xFFFF Lower sector = 0x1100 - 0x7FFF Upper sector = 0x8000 - 0xFFFF Lower sector = 0x1100 - 0x9FFF Upper sector = 0xA000 - 0xFFFF Lower sector = 0x1100 - 0xBFFF Upper sector = 0xC000 - 0xFFFF Lower sector = 0x1100 - 0xDFFF Upper sector = 0xE000 - 0xFFFF
* Bit 1 and Bit 6 MCUCR - SRW11, SRW10: Wait State Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait states for the upper sector of the external memory address space, see Table 4. * Bit 3..2 - SRW01, SRW00: Wait State Select Bits for Lower Sector The SRW01 and SRW00 bits control the number of wait states for the lower sector of the external memory address space, see Table 4. Table 4. Wait States(1)
SRWn1 0 0 1 1 Note: SRWn0 0 1 0 1 Wait States No wait states Wait one cycle during read/write strobe Wait two cycles during read/write strobe Wait two cycles during read/write and wait one cycle before driving out new address
1. n = 0 or 1 (lower/upper sector). For further details of the timing and wait states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.
* Bit 0 - Res: Reserved Bit This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for compatibility with future devices.
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XMCRB - External Memory Control Register B
Bit (0x6C) Read/Write Initial Value
7 XMBK R/W 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 XMM2 R/W 0
1 XMM1 R/W 0
0 XMM0 R/W 0 XMCRB
* Bit 7 - XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables the Bus Keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the Bus Keepers are still activated as long as XMBK is one. * Bit 6..3 - Res: Reserved Bits These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices. * Bit 2..0 - XMM2, XMM1, XMM0: External Memory High Mask When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal port pin function as described in Table 5. As described in "Using all 64KB Locations of External Memory" on page 36, it is possible to use the XMMn bits to access all 64KB locations of the external memory. Table 5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMM2 0 0 0 0 1 1 1 1 XMM1 0 0 1 1 0 0 1 1 XMM0 0 1 0 1 0 1 0 1 # Bits for External Memory Address 8 (Full 60 KB space) 7 6 5 4 3 2 No Address high bits Released Port Pins None PC7 PC7 - PC6 PC7 - PC5 PC7 - PC4 PC7 - PC3 PC7 - PC2 Full Port C
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Using all Locations of External Memory Smaller than 64 KB Since the external memory is mapped after the internal memory as shown in Figure 11, the external memory is not addressed when addressing the first 4,352 bytes of data space. It may appear that the first 4,352 bytes of the external memory are inaccessible (external memory addresses 0x0000 to 0x10FF). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessed simply by addressing from address 0x8000 to 0x90FF. Since the External Memory Address bit A15 is not connected to the external memory, addresses 0x8000 to 0x90FF will appear as addresses 0x0000 to 0x10FF for the external memory. Addressing above address 0x90FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x1100 to 0x90FF. This is illustrated in Figure 17. Memory configuration B refers to the ATmega103 compatibility mode, configuration A to the non-compatible mode. When the device is set in ATmega103 compatibility mode, the internal address space is 4,096 bytes. This implies that the first 4,096 bytes of the external memory can be accessed at addresses 0x8000 to 0x8FFF. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x1000 to 0x8FFF. Figure 17. Address Map with 32 KB External Memory
Memory Configuration A
AVR Memory Map External 32K SRAM
Memory Configuration B
AVR Memory Map External 32K SRAM
0x0000 Internal Memory 0x10FF 0x1100
0x0000
0x0000 0x0FFF 0x1000 Internal Memory
0x0000 0x0FFF 0x1000
0x10FF 0x1100
0x7FFF 0x8000
External Memory
0x7FFF
0x7FFF 0x8000
External Memory
0x7FFF
0x90FF 0x9100
0x8FFF 0x9000
(Unused)
(Unused)
0xFFFF
0xFFFF
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Using all 64KB Locations of External Memory
Since the external memory is mapped after the internal memory as shown in Figure 11, only 60KB of external memory is available by default (address space 0x0000 to 0x10FF is reserved for internal memory). However, it is possible to take advantage of the entire external memory by masking the higher address bits to zero. This can be done by using the XMMn bits and controlled by software the most significant bits of the address. By setting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation, the Memory Interface will address 0x0000 - 0x1FFF. See code examples below. Assembly Code Example(1)
; ; ; ; ; OFFSET is defined to 0x2000 to ensure external memory access Configure Port C (address high byte) to output 0x00 when the pins are released for normal Port Pin operation
ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; release PC7:5 ldi r16, (1<C Code Example(1)
#define OFFSET 0x2000 void XRAM_example(void) { unsigned char *p = (unsigned char *) (OFFSET + 1); DDRC = 0xFF; PORTC = 0x00; XMCRB = (1<Note:
1. See "About Code Examples" on page 9.
Care must be exercised using this option as most of the memory is masked away.
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System Clock and Clock Options
Clock Systems and their Distribution
Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in "Power Management and Sleep Modes" on page 46. The clock systems are detailed below. Figure 18. Clock Distribution
Asynchronous Timer/Counter General I/O Modules ADC CPU Core RAM Flash and EEPROM
clkADC clkI/O clkASY clkCPU clkFLASH
AVR Clock Control Unit
Reset Logic
Watchdog Timer
Source Clock Clock Multiplexer
Watchdog Clock Watchdog Oscillator
Timer/Counter Oscillator
External RC Oscillator
External Clock
Crystal Oscillator
Low-frequency Crystal Oscillator
Calibrated RC Oscillator
CPU Clock - clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchronously when clkI/O is halted, enabling TWI address reception in all sleep modes. The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.
I/O Clock - clkI/O
Flash Clock - clkFLASH
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Asynchronous Timer Clock - clkASY ADC Clock - clkADC
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6. Device Clocking Options Select(1)
Device Clocking Option External Crystal/Ceramic Resonator External Low-frequency Crystal External RC Oscillator Calibrated Internal RC Oscillator External Clock Note: CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000
Clock Sources
1. For all fuses "1" means unprogrammed while "0" means programmed.
The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7. The frequency of the Watchdog Oscillator is voltage dependent as shown in the "Typical Characteristics" on page 342. Table 7. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V) 4.1 ms 65 ms Typ Time-out (VCC = 3.0V) 4.3 ms 69 ms Number of Cycles 4K (4,096) 64K (65,536)
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XDIV - XTAL Divide Control Register The XTAL Divide Control Register is used to divide the source clock frequency by a number in the range 2 - 129. This feature can be used to decrease power consumption when the requirement for processing power is low.
Bit 0x3C (0x5C) Read/Write Initial Value 7 XDIVEN R/W 0 6 XDIV6 R/W 0 5 XDIV5 R/W 0 4 XDIV4 R/W 0 3 XDIV3 R/W 0 2 XDIV2 R/W 0 1 XDIV1 R/W 0 0 XDIV0 R/W 0 XDIV
* Bit 7 - XDIVEN: XTAL Divide Enable When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clkI/O, clkADC, clkCPU, clkFLASH) is divided by the factor defined by the setting of XDIV6 XDIV0. This bit can be written run-time to vary the clock frequency as suitable to the application. * Bits 6..0 - XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0 These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of these bits is denoted d, the following formula defines the resulting CPU and peripherals clock frequency fclk: f CLK = Source clock --------------------------------129 - d The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to one, the value written simultaneously into XDIV6..XDIV0 is taken as the division factor. When XDIVEN is written to zero, the value written simultaneously into XDIV6..XDIV0 is rejected. As the divider divides the master clock input to the MCU, the speed of all peripherals is reduced when a division factor is used.
Note: When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail.
Default Clock Source
The device is shipped with CKSEL = "0001" and SUT = "10". The default clock source setting is therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an InSystem or Parallel Programmer. XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a full rail-to-rail swing on the output. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces power consumption considerably. This mode has a limited frequency range and it cannot be used to drive other clock buffers. For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in 39
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Table 8. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 19. Crystal Oscillator Connections
C2 C1
XTAL2 XTAL1 GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8. Table 8. Crystal Oscillator Operating Modes
CKOPT 1 1 1 0 Note: CKSEL3..1 101(1) 110 111 101, 110, 111 Frequency Range (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 1.0 Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) - 12 - 22 12 - 22 12 - 22
1. This option should not be used with crystals, only with ceramic resonators.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 9.
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Table 9. Start-up Times for the Crystal Oscillator Clock Selection
Start-up Time from Power-down and Power-save 258 CK(1) 258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK Additional Delay from Reset (VCC = 5.0V) 4.1 ms 65 ms - 4.1 ms 65 ms - 4.1 ms 65 ms
CKSEL0 0 0 0 0 1 1 1 1 Notes:
SUT1..0 00 01 10 11 00 01 10 11
Recommended Usage Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power
1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
Low-frequency Crystal Oscillator
To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency crystal Oscillator must be selected by setting the CKSEL Fuses to "1001". The crystal should be connected as shown in Figure 19. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36 pF. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10. Table 10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
Start-up Time from Power-down and Power-save 1K CK(1) 1K CK
(1)
SUT1..0 00 01 10 11 Note:
Additional Delay from Reset (VCC = 5.0V) 4.1 ms 65 ms 65 ms Reserved
Recommended Usage Fast rising power or BOD enabled Slowly rising power Stable frequency at start-up
32K CK
1. These options should only be used if frequency stability at start-up is not important for the application.
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External RC Oscillator
For timing insensitive applications, the external RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 20. External RC Configuration
VCC NC
R
XTAL2 XTAL1
C GND
The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 11. Table 11. External RC Oscillator Operating Modes
CKSEL3..0 0101 0110 0111 1000 Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 12. Table 12. Start-up Times for the External RC Oscillator Clock Selection
Start-up Time from Power-down and Power-save 18 CK 18 CK 18 CK 6 CK
(1)
SUT1..0 00 01 10 11 Note:
Additional Delay from Reset (VCC = 5.0V) - 4.1 ms 65 ms 4.1 ms
Recommended Usage BOD enabled Fast rising power Slowly rising power Fast rising power or BOD enabled
1. This option should not be used when operating close to the maximum frequency of the device.
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Calibrated Internal RC Oscillator
The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 13. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 5V, 25C and 1.0 MHz Oscillator frequency selected, this calibration gives a frequency within 3% of the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve 1% accuracy at any given VCC and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the preprogrammed calibration value, see the section "Calibration Byte" on page 294. Table 13. Internal Calibrated RC Oscillator Operating Modes
CKSEL3..0 0001(1) 0010 0011 0100 Note: 1. The device is shipped with this option selected. Nominal Frequency (MHz) 1.0 2.0 4.0 8.0
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 14. XTAL1 and XTAL2 should be left unconnected (NC). Table 14. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
SUT1..0 00 01 10
(1)
Start-up Time from Powerdown and Power-save 6 CK 6 CK 6 CK
Additional Delay from Reset (VCC = 5.0V) - 4.1 ms 65 ms Reserved
Recommended Usage BOD enabled Fast rising power Slowly rising power
11 Note:
1. The device is shipped with this option selected.
OSCCAL - Oscillator Calibration Register(1)
Bit (0x6F) Read/Write Initial Value
7 CAL7 R/W
6 CAL6 R/W
5 CAL5 R/W
4 CAL4 R/W
3 CAL3 R/W
2 CAL2 R/W
1 CAL1 R/W
0 CAL0 R/W OSCCAL
Device Specific Calibration Value
Note:
1. The OSCCAL Register is not available in ATmega103 compatibility mode.
* Bits 7..0 - CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. During Reset, the 1 MHz calibration value which is located in the signature row high byte (address 0x00) is automatically loaded into the OSCCAL Register. If the internal RC is used at other frequencies, the calibration values must be loaded manually. This can be done by first reading the signature row by a programmer, and then store the calibration values in the Flash or EEPROM. Then the
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value can be read by software and loaded into the OSCCAL Register. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 15. Table 15. Internal RC Oscillator Frequency Range
OSCCAL Value 0x00 0x7F 0xFF Min Frequency in Percentage of Nominal Frequency (%) 50 75 100 Max Frequency in Percentage of Nominal Frequency (%) 100 150 200
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 21. To run the device on an external clock, the CKSEL Fuses must be programmed to "0000". By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND. Figure 21. External Clock Drive Configuration
EXTERNAL CLOCK SIGNAL
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 16. Table 16. Start-up Times for the External Clock Selection
SUT1..0 00 01 10 11 Start-up Time from Powerdown and Power-save 6 CK 6 CK 6 CK Additional Delay from Reset (VCC = 5.0V) - 4.1 ms 65 ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is
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required to ensure that the MCU is kept in Reset during such changes in the clock frequency.
Timer/Counter Oscillator
For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended.
Note: The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF.
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Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. To enter any of the six sleep modes, the SE-bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction. See Table 17 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 18 on page 37 presents the different clock systems in the ATmega64, and their distribution. This figure is helpful in selecting an appropriate sleep mode.
MCUCR - MCU Control Register
The MCU Control Register contains control bits for power management.
Bit 0x35 (0x55) Read/Write Initial Value 7 SRE R/W 0 6 SRW10 R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 SM2 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* Bit 5 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. * Bits 4..2 - SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the six available sleep modes as shown in Table 17. Table 17. Sleep Mode Select
SM2 0 0 0 0 1 1 1 1 Note: SM1 0 0 1 1 0 0 1 1 SM0 0 1 0 1 0 1 0 1 Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved Standby(1) Extended Standby(1)
1. Standby mode and Extended Standby mode are only available with external crystals or resonators.
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Idle Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Twowire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register - ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
ADC Noise Reduction Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the Two-wire Serial Interface address watch, Timer/Counter0 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk I/O, clkCPU, and clk-FLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter0 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU from ADC Noise Reduction mode.
Power-down Mode
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, an external level interrupt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to "External Interrupts" on page 90 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in "Clock Sources" on page 38.
Power-save Mode
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, with one exception: If Timer/Counter0 is clocked asynchronously (i.e., the AS0 bit in ASSR is set), Timer/Counter0 will run during sleep. The device can wake up from either Timer Overflow o r Ou tput Comp are event from Tim er/Coun ter0 if the corre sp ond ing Timer/Counter0 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in SREG is set. If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the 47
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asynchronous timer should be considered undefined after wake-up in Power-save mode if AS0 is 0. This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules, including Timer/Counter0 if clocked asynchronously.
Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles.
Extended Standby Mode
Table 18. Active Clock Domains and Wake Up Sources in the Different Sleep Modes
Active Clock Domains clkFLASH Oscillators TWI Address Match Main Clock Source Enabled Timer Osc Enabled Wake Up Sources SPM/ EEPROM Ready Timer0
clkCPU
clkADC
clkASY
Sleep Mode Idle ADC Noise Reduction Powerdown Powersave Standby(1) Extended Standby(1) Notes:
X
X X
X X
X X
X(2) X(2)
X X(3)
X X
X X
X X
X X
X(3) X(2) X X(2) X X(2) X(2) X(3) X(3) X(3)
X X X X X(2) X(2)
1. External Crystal or resonator selected as clock source. 2. If AS0 bit in ASSR is set. 3. Only INT3:0 or level interrupt INT7:4.
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Other I/O X
clkIO
I N
A
ATmega64(L)
Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to "Analog to Digital Converter" on page 231 for details on ADC operation. When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the internal voltage reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be enabled, independent of sleep mode. Refer to "Analog Comparator" on page 228 for details on how to configure the Analog Comparator. If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to "Brown-out Detector" on page 49 for details on how to configure the Brown-out Detector. The internal voltage reference will be enabled when needed by the Brown-out Detector, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to "Internal Voltage Reference" on page 56 for details on the start-up time. If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to "Watchdog Timer" on page 56 for details on how to configure the Watchdog Timer. When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section "Digital Input Enable and Sleep Modes" on page 70 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power.
Analog to Digital Converter
Analog Comparator
Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
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JTAG Interface and On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: * * * Disable OCDEN Fuse. Disable JTAGEN Fuse. Write one to the JTD bit in MCUCSR.
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface.
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System Control and Reset
Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP - absolute jump - instruction to the Reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 22 shows the Reset logic. Table 19 defines the electrical parameters of the Reset circuitry. The I/O ports of the AVR are immediately Reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the Internal Reset. This allows the power to reach a stable level before normal operation starts. The Time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in "Clock Sources" on page 38. Reset Sources The ATmega64 has five sources of reset: * * * * * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled. JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section "IEEE 1149.1 (JTAG) Boundary-scan" on page 255 for details.
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Figure 22. Reset Logic
DATA BUS
PEN
D L Pull-up Resistor
Q Q
MCU Control and Status Register (MCUCSR)
PORF BORF EXTRF WDRF JTRF
Power-On Reset Circuit
BODEN BODLEVEL Pull-up Resistor RESET
SPIKE FILTER
Brown-Out Reset Circuit
Reset Circuit
JTAG Reset Register
Watchdog Timer
Watchdog Oscillator
Clock Generator
CK
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
Table 19. Reset Characteristics
Symbol Parameter Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling)(1) RESET Pin Threshold Voltage Minimum pulse width on RESET Pin Brown-out Reset Threshold Voltage(2) Minimum low voltage period for Brown-out Detection Brown-out Detector hysteresis BODLEVEL = 1 BODLEVEL = 0 BODLEVEL = 1 BODLEVEL = 0 2.5 3.6 2.7 4.0 2 2 120 0.2 VCC Condition Min Typ 1.4 Max 2.3 Units V
1.3
COUNTER RESET
2.3
V
VRST tRST VBOT
0.85 VCC 1.5 2.9
V s
V 4.2 s s mV
tBOD
VHYST
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Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). 2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega64L and BODLEVEL=0 for ATmega64. BODLEVEL=1 is not applicable for ATmega64.
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detection level is defined in Table 19. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Figure 23. MCU Start-up, RESET Tied to VCC
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure 24. MCU Start-up, RESET Extended Externally
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
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External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 19) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired. Figure 25. External Reset during Operation
CC
Brown-out Detection
ATmega64 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and VCC decreases to a value below the trigger level (VBOT- in Figure 26), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 26), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 19. Figure 26. Borwn-out Reset During Operation
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 56 for details on operation of the Watchdog Timer. Figure 27. Watchdog Reset During Operation
CC
CK
MCUCSR - MCU Control and Status Register(1)
The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
Bit 0x34 (0x54) Read/Write Initial Value 7 JTD R/W 0 6 - R 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W See Bit Description 1 EXTRF R/W 0 PORF R/W MCUCSR
Note:
1. Only EXTRF and PORF are available in mega103 compatibility mode.
* Bit 4 - JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset, or by writing a logic zero to the flag. * Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
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* Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.
Internal Voltage Reference
Voltage Reference Enable Signals and Start-up Time
ATmega64 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 20. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODEN Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Table 20. Internal Voltage Reference Characteristics
Symbol VBG tBG IBG Parameter Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption Min 1.15 Typ 1.23 40 10 Max 1.35 70 Units V s A
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 22 on page 58. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega64 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 55. To prevent unintentional disabling of the Watchdog or unintentional change of Time-out period, three different safety levels are selected by the fuses M103C and WDTON as shown in Table 21. Safety level 0 corresponds to the setting in ATmega103. There is no restriction on enabling the WDT in any of the safety levels. Refer to "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 60 for details.
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Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON
Safety Level 1 2 0 2 WDT Initial State Disabled Enabled Disabled Enabled How to Disable the WDT Timed sequence Always enabled Timed sequence Always enabled How to Change Time-out Timed sequence Timed sequence No restriction Timed sequence
M103C Unprogrammed Unprogrammed Programmed Programmed
WDTON Unprogrammed Programmed Unprogrammed Programmed
Figure 28. Watchdog Timer
WATCHDOG OSCILLATOR
WDTCR - Watchdog Timer Control Register
Bit 0x21 (0x41) Read/Write Initial Value
7 - R 0
6 - R 0
5 - R 0
4 WDCE R/W 0
3 WDE R/W 0
2 WDP2 R/W 0
1 WDP1 R/W 0
0 WDP0 R/W 0 WDTCR
* Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the ATmega64 and will always read as zero. * Bit 4 - WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 60.
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* Bit 3 - WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 60. * Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 22. Table 22. Watchdog Timer Prescale Select
WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 Number of WDT Oscillator Cycles 16K (16,384) 32K (32,768) 64K (65,536) 128K (131,072) 256K (262,144) 512K (524,288) 1,024K (1,048,576) 2,048K (2,097,152) Typical Time-out at VCC = 3.0V 17.1 ms 34.3 ms 68.5 ms 0.14 s 0.27 s 0.55 s 1.1 s 2.2 s Typical Time-out at VCC = 5.0V 16.3 ms 32.5 ms 65 ms 0.13 s 0.26 s 0.52 s 1.0 s 2.1 s
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The following code examples show one assembly and one C function for turning off the WDT. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example
WDT_off: ; reset WDT
wdr in r16, WDTCR ldi r16, (1<; Write logical one to WDCE and WDE ori out ldi out ret r16, (1<; Turn off WDT
C Code Example
void WDT_off(void) { /* Reset WDT*/ _WDRC(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<59
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Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 0
The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level.
This mode is compatible with the Watchdog operation found in ATmega103. The Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. The Time-out period can be changed at any time without restriction. To disable an enabled Watchdog Timer, the procedure described on page 58 (WDE bit description) must be followed. In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared.
Safety Level 1
Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
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Interrupts
This section describes the specifics of the interrupt handling as performed in ATmega64. For a general explanation of the AVR interrupt handling, refer to "Reset and Interrupt Handling" on page 15.
Interrupt Vectors in ATmega64
Table 23. Reset and Interrupt Vectors
Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Program Address(2) 0x0000
(1)
Source RESET INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMP TIMER0 OVF SPI, STC USART0, RX USART0, UDRE USART0, TX ADC EE READY ANALOG COMP TIMER1 COMPC TIMER3 CAPT TIMER3 COMPA TIMER3 COMPB TIMER3 COMPC TIMER3 OVF USART1, RX
Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset External Interrupt Request 0 External Interrupt Request 1 External Interrupt Request 2 External Interrupt Request 3 External Interrupt Request 4 External Interrupt Request 5 External Interrupt Request 6 External Interrupt Request 7 Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Compare Match Timer/Counter0 Overflow SPI Serial Transfer Complete USART0, Rx Complete USART0 Data Register Empty USART0, Tx Complete ADC Conversion Complete EEPROM Ready Analog Comparator Timer/Countre1 Compare Match C Timer/Counter3 Capture Event Timer/Counter3 Compare Match A Timer/Counter3 Compare Match B Timer/Counter3 Compare Match C Timer/Counter3 Overflow USART1, Rx Complete
0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030(3) 0x0032 0x0034 0x0036
(3) (3) (3)
0x0038(3) 0x003A
(3) (3)
0x003C
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Table 23. Reset and Interrupt Vectors (Continued)
Vector No. 32 33 34 35 Notes: Program Address(2) 0x003E(3) 0x0040(3) 0x0042 0x0044
(3) (3)
Source USART1, UDRE USART1, TX TWI SPM READY
Interrupt Definition USART1 Data Register Empty USART1, Tx Complete Two-wire Serial Interface Store Program Memory Ready
1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see "Boot Loader Support - Read-While-Write Self-programming" on page 278. 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash section. The address of each Interrupt Vector will then be address in this table added to the start address of the Boot Flash section. 3. The Interrupts on address 0x0030 - 0x0044 do not exist in ATmega103 compatibility mode.
Table 24 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 24. Reset and Interrupt Vectors Placement(1)
BOOTRST 1 1 0 0 Note: IVSEL 0 1 0 1 Reset Address 0x0000 0x0000 Boot Reset Address Boot Reset Address Interrupt Vectors Start Address 0x0002 Boot Reset Address + 0x0002 0x0002 Boot Reset Address + 0x0002
1. The Boot Reset Address is shown in Table 112 on page 290. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega64 is:
Address Labels Code 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET EXT_INT0 EXT_INT1 EXT_INT2 EXT_INT3 EXT_INT4 EXT_INT5 EXT_INT6 EXT_INT7 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; IRQ2 Handler ; IRQ3 Handler ; IRQ4 Handler ; IRQ5 Handler ; IRQ6 Handler ; IRQ7 Handler ; Timer2 Compare Handler ; Timer2 Overflow Handler ; Timer1 Capture Handler ; Timer1 CompareA Handler ; Timer1 CompareB Handler ; Timer1 Overflow Handler
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0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 0x0034 0x0036 0x0038 0x003A 0x003C 0x003E 0x0040 0x0042 0x0044 ; 0x0046 RESET: ldi 0x0047 0x0048 0x0049 0x004A 0x004B ... ... out ldi out sei ... r16, high(RAMEND); Main program start SPH,r16 SPL,r16 ; Enable interrupts xxx ... ; Set Stack Pointer to top of RAM r16, low(RAMEND) jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp TIM0_COMP TIM0_OVF SPI_STC USART0_RXC USART0_DRE USART0_TXC ADC EE_RDY ANA_COMP TIM1_COMPC TIM3_CAPT TIM3_COMPA TIM3_COMPB TIM3_COMPC TIM3_OVF USART1_RXC USART1_DRE USART1_TXC TWI SPM_RDY ; Timer0 Compare Handler ; Timer0 Overflow Handler ; SPI Transfer Complete Handler ; USART0 RX Complete Handler ; USART0,UDR Empty Handler ; USART0 TX Complete Handler ; ADC Conversion Complete Handler ; EEPROM Ready Handler ; Analog Comparator Handler ; Timer1 CompareC Handler ; Timer3 Capture Handler ; Timer3 CompareA Handler ; Timer3 CompareB Handler ; Timer3 CompareC Handler ; Timer3 Overflow Handler ; USART1 RX Complete Handler ; USART1,UDR Empty Handler ; USART1 TX Complete Handler ; Two-wire Serial Interface Handler ; SPM Ready Handler
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code 0x0000 RESET: ldi 0x0001 0x0002 0x0003 0x0004 0x0005 ; .org 0x7002 0x7002 0x7004 ... 0x7044 jmp jmp ... jmp EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler out ldi out sei SPH,r16 SPL,r16 ; Enable interrupts xxx Comments r16,high(RAMEND); Main program start ; Set Stack Pointer to top of RAM r16,low(RAMEND)
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When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code .org 0x0002 0x0002 0x0004 ... 0x0044 ; .org 0x7000 0x7000 RESET: ldi 0x7001 0x7002 0x7003 0x7004 0x7005 out ldi out sei r16,high(RAMEND); Main program start SPH,r16 SPL,r16 ; Enable interrupts xxx ; Set Stack Pointer to top of RAM r16,low(RAMEND) jmp jmp ... jmp EXT_INT0 ; IRQ0 Handler EXT_INT1 ; IRQ1 Handler ... SPM_RDY ; ; Store Program Memory Ready Handler Comments
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code ; .org 0x7000 0x7000 0x7002 0x7004 ... 0x7044 0x7047 0x7048 0x7049 0x704A 0x704B jmp jmp jmp ... jmp out ldi out sei RESET ; Reset handler EXT_INT0 ; IRQ0 Handler EXT_INT1 ; IRQ1 Handler ... ; SPM_RDY ; Store Program Memory Ready Handler r16,high(RAMEND); Main program start SPH,r16 SPL,r16 ; Enable interrupts xxx ; Set Stack Pointer to top of RAM r16,low(RAMEND) Comments
0x7046 RESET: ldi
Moving Interrupts Between Application and Boot Space MCUCR - MCU Control Register
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
Bit 0x35 (0x55) Read/Write Initial Value
7 SRE R/W 0
6 SRW10 R/W 0
5 SE R/W 0
4 SM1 R/W 0
3 SM0 R/W 0
2 SM2 R/W 0
1 IVSEL R/W 0
0 IVCE R/W 0 MCUCR
* Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot
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Flash section is determined by the BOOTSZ Fuses. Refer to the section "Boot Loader Support - Read-While-Write Self-programming" on page 278 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section "Boot Loader Support - Read-While-Write Self-programming" on page 278 for details on Boot Lock bits.
* Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See code examples below. Assembly Code Example
Move_interrupts: ; Enable change of Interrupt Vectors ldi out ldi out ret r16, (1<; Move interrupts to boot Flash section
C Code Example
void Move_interrupts(void) { /* Enable change of Interrupt Vectors */ MCUCR = (1<65
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I/O Ports
Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 29. Refer to "Electrical Characteristics" on page 327 for a complete list of parameters. Figure 29. I/O Pin Equivalent Schematic
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used (i.e., PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn). The physical I/O Registers and bit locations are listed in "Register Description for I/O Ports" on page 87. Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. In addition, the Pull-up Disable - PUD bit in SFIOR disables the pull-up function for all pins in all ports when set. Using the I/O port as general digital I/O is described in "Ports as General Digital I/O" on page 67. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in "Alternate Port Functions" on page 71. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.
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Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 30. General Digital I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx
RDx
Pxn
Q
D
PORTxn Q CLR
WPx RESET SLEEP RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WPx: RRx: RPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN
Note:
1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports.
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in "Register Description for I/O Ports" on page 87, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
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When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to one to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 25 summarizes the control signals for the pin value. Table 25. Port Pin Configurations
DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD (in SFIOR) X 0 1 X X I/O Input Input Input Output Output Pull-up No Yes No No No Comment Tri-state (Hi-Z) Pxn will source current if ext. pulled low. Tri-state (Hi-Z) Output Low (Sink) Output High (Source)
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 31 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 31. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 tpd, max tpd, min 0xFF XXX XXX in r17, PINx
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 1-1/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 32. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 32. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 tpd 0xFF out PORTx, r16 nop 0xFF
in r17, PINx
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The following code example show how to set Port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1)
... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out nop ; Read port pins in ... r16,PINB r16,(1<; Insert nop for synchronization
C Code Example
unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<Note:
1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
Digital Input Enable and Sleep Modes
As shown in Figure 30, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, Standby mode, and Extended Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as External Interrupt pins. If the External Interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in "Alternate Port Functions" on page 71. If a logic high level ("one") is present on an asynchronous External Interrupt pin configured as "Interrupt on Any Logic Change on Pin" while the External Interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change.
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Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 33 shows how the port pin control signals from the simplified Figure 30 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 33. Alternate Port Functions(1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D PORTxn
DIEOExn DIEOVxn
1 0
Q CLR
WPx RESET RRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL
PUD: WDx: RDx: RRx: WPx: RPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 26 summarizes the function of the overriding signals. The pin and port indexes from Figure 33 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
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Table 26. Generic Description of Overriding Signals for Alternate Functions
Signal Name PUOE Full Name Pull-up Override Enable Pull-up Override Value Data Direction Override Enable Data Direction Override Value Port Value Override Enable Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep modes). If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep modes). This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the Schmitt Trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally.
PUOV
DDOE
DDOV
PVOE
PVOV DIEOE
Port Value Override Value Digital Input Enable Override Enable
DIEOV
Digital Input Enable Override Value Digital Input
DI
AIO
Analog Input/output
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. SFIOR - Special Function IO Register
Bit 0x20 (0x40) Read/Write Initial Value
7 TSM R/W 0
6 - R 0
5 - R 0
4 - R 0
3 ACME R/W 0
2 PUD R/W 0
1 PSR0 R/W 0
0 PSR321 R/W 0 SFIOR
* Bit 2 - PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See "Configuring the Pin" on page 67 for more details about this feature.
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Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 27. Port A Pins Alternate Functions
Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Alternate Function AD7 (External memory interface address and data bit 7) AD6 (External memory interface address and data bit 6) AD5 (External memory interface address and data bit 5) AD4 (External memory interface address and data bit 4) AD3 (External memory interface address and data bit 3) AD2 (External memory interface address and data bit 2) AD1 (External memory interface address and data bit 1) AD0 (External memory interface address and data bit 0)
Table 28 and Table 29 relates the alternate functions of Port A to the overriding signals shown in Figure 33 on page 71. Table 28. Overriding Signals for Alternate Functions in PA7..PA4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PA7/AD7
SRE ~(WR | ADA ) * PORTA7 * PUD SRE WR | ADA SRE A7 * ADA | D7 OUTPUT * WR 0 0 D7 INPUT -
(1)
PA6/AD6
SRE ~(WR | ADA) * PORTA6 * PUD SRE WR | ADA SRE A6 * ADA | D6 OUTPUT * WR 0 0 D6 INPUT -
PA5/AD5
SRE ~(WR | ADA) * PORTA5 * PUD SRE WR | ADA SRE A5 * ADA | D5 OUTPUT * WR 0 0 D5 INPUT -
PA4/AD4
SRE ~(WR | ADA) * PORTA4 * PUD SRE WR | ADA SRE A4 * ADA | D4 OUTPUT * WR 0 0 D4 INPUT -
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Table 29. Overriding Signals for Alternate Functions in PA3..PA0(1)
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PA3/AD3
SRE ~(WR | ADA) * PORTA3 * PUD SRE WR | ADA SRE A3 * ADA | D3 OUTPUT * WR 0 0 D3 INPUT -
PA2/AD2
SRE ~(WR | ADA) * PORTA2 * PUD SRE WR | ADA SRE A2* ADA | D2 OUTPUT * WR 0 0 D2 INPUT -
PA1/AD1
SRE ~(WR | ADA) * PORTA1 * PUD SRE WR | ADA SRE A1 * ADA | D1 OUTPUT * WR 0 0 D1 INPUT -
PA0/AD0
SRE ~(WR | ADA) * PORTA0 * PUD SRE WR | ADA SRE A0 * ADA | D0 OUTPUT * WR 0 0 D0 INPUT -
1. ADA is short for ADdress Active and represents the time when address is output. See "External Memory Interface" on page 27 for details.
Alternate Functions of Port B
The Port B pins with alternate functions are shown in Table 30. Table 30. Port B Pins Alternate Functions
Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Note: Alternate Functions OC2/OC1C(1) (Output Compare and PWM Output for Timer/Counter2 or Output Compare and PWM Output C for Timer/Counter1) OC1B (Output Compare and PWM Output B for Timer/Counter1) OC1A (Output Compare and PWM Output A for Timer/Counter1) OC0 (Output Compare and PWM Output for Timer/Counter0) MISO (SPI Bus Master Input/Slave Output) MOSI (SPI Bus Master Output/Slave Input) SCK (SPI Bus Serial Clock) SS (SPI Slave Select input) 1. OC1C not applicable in ATmega103 compatibility mode.
The alternate pin configuration is as follows: * OC2/OC1C, Bit 7 OC2, Output Compare Match output: The PB7 pin can serve as an external output for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function. OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function. 74
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* OC1B, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. * OC1A, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. * OC0, Bit 4 OC0, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. * MISO - Port B, Bit 3 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. * MOSI - Port B, Bit 2 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. * SCK - Port B, Bit 1 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. * SS - Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. Table 31 and Table 32 relate the alternate functions of Port B to the overriding signals shown in Figure 33 on page 71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
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Table 31. Overriding Signals for Alternate Functions in PB7..PB4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PB7/OC2/OC1C 0 0 0 0 OC2/OC1C ENABLE OC2/OC1C 0 0 - -
(1) (1)
PB6/OC1B 0 0 0 0 OC1B ENABLE OC1B 0 0 - -
PB5/OC1A 0 0 0 0 OC1A ENABLE OC1A 0 0 - -
PB4/OC0 0 0 0 0 OC0 ENABLE OC0B 0 0 - -
1. See "Output Compare Modulator (OCM1C2)" on page 161 for details. OC1C does not exist in ATmega103 compatibility mode.
Table 32. Overriding Signals for Alternate Functions in PB3..PB0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB3/MISO SPE * MSTR PORTB3 * PUD SPE * MSTR 0 SPE * MSTR SPI SLAVE OUTPUT 0 0 SPI MSTR INPUT - PB2/MOSI SPE * MSTR PORTB2 * PUD SPE * MSTR 0 SPE * MSTR SPI MSTR OUTPUT 0 0 SPI SLAVE INPUT - PB1/SCK SPE * MSTR PORTB1 * PUD SPE * MSTR 0 SPE * MSTR SCK OUTPUT 0 0 SCK INPUT - PB0/SS SPE * MSTR PORTB0 * PUD SPE * MSTR 0 0 0 0 0 SPI SS -
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Alternate Functions of Port C In ATmega103 compatibility mode, Port C is output only. The Port C has an alternate function as the address high byte for the External Memory Interface Table 33. Port C Pins Alternate Functions
Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Alternate Function A15 A14 A13 A12 A11 A10 A9 A8
Table 34 and Table 35 relate the alternate functions of Port C to the overriding signals shown in Figure 33 on page 71. Table 34. Overriding Signals for Alternate Functions in PC7..PC4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PC7/A15 SRE * (XMM <1) 0 SRE * (XMM<1) 1 SRE * (XMM<1) A11 0 0 - -
(1)
PC6/A14 SRE * (XMM<2) 0 SRE * (XMM<2) 1 SRE * (XMM<2) A10 0 0 - -
PC5/A13 SRE * (XMM<3) 0 SRE * (XMM<3) 1 SRE * (XMM<3) A9 0 0 - -
PC4/A12 SRE * (XMM<4) 0 SRE * (XMM<4) 1 SRE * (XMM<4) A8 0 0 - -
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Table 35. Overriding Signals for Alternate Functions in PC3..PC0(1)
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PC3/A11 SRE * (XMM<5) 0 SRE * (XMM<5) 1 SRE * (XMM<5) A11 0 0 - - PC2/A10 SRE * (XMM<6) 0 SRE * (XMM<6) 1 SRE * (XMM<6) A10 0 0 - - PC1/A9 SRE * (XMM<7) 0 SRE * (XMM<7) 1 SRE * (XMM<7) A9 0 0 - - PC0/A8 SRE * (XMM<7) 0 SRE * (XMM<7) 1 SRE * (XMM<7) A8 0 0 - -
1. XMM = 0 in ATmega103 compatibility mode.
Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 36. Table 36. Port D Pins Alternate Functions
Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Note: Alternate Function T2 (Timer/Counter2 Clock Input) T1 (Timer/Counter1 Clock Input) XCK1(1) (USART1 External Clock Input/Output) ICP1 (Timer/Counter1 Input Capture Pin) INT3/TXD1(1) (External Interrupt3 Input or UART1 Transmit Pin) INT2/RXD1(1) (External Interrupt2 Input or UART1 Receive Pin) INT1/SDA(1) (External Interrupt1 Input or TWI Serial DAta) INT0/SCL(1) (External Interrupt0 Input or TWI Serial CLock)
1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.
The alternate pin configuration is as follows: * T2 - Port D, Bit 7 T2, Timer/Counter2 Counter Source. * T1 - Port D, Bit 6 T1, Timer/Counter1 Counter Source. * XCK1 - Port D, Bit 5 XCK1, USART1 External Clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1 operates in synchronous mode.
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* ICP1 - Port D, Bit 4 ICP1 - Input Capture Pin1: The PD4 pin can act as an Input Capture pin for Timer/Counter1. * INT3/TXD1 - Port D, Bit 3 INT3, External Interrupt Source 3: The PD3 pin can serve as an External Interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. * INT2/RXD1 - Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit. * INT1/SDA - Port D, Bit 1 INT1, External Interrupt Source 1. The PD1 pin can serve as an External Interrupt source to the MCU. SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD1 is disconnected from the port and becomes the serial data I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. * INT0/SCL - Port D, Bit 0 INT0, External Interrupt Source 0. The PD0 pin can serve as an External Interrupt source to the MCU. SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD0 is disconnected from the port and becomes the serial clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals shown in Figure 33 on page 71.
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Table 37. Overriding Signals for Alternate Functions PD7..PD4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PD7/T2 0 0 0 0 0 0 0 0 T2 INPUT - PD6/T1 0 0 0 0 0 0 0 0 T1 INPUT - PD5/XCK1 0 0 0 0 UMSEL1 XCK1 OUTPUT 0 0 XCK1 INPUT - PD4/ICP1 0 0 0 0 0 0 0 0 ICP1 INPUT -
Table 38. Overriding Signals for Alternate Functions in PD3..PD0(1)
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PD3/INT3/TXD1 TXEN1 0 TXEN1 1 TXEN1 TXD1 INT3 ENABLE 1 INT3 INPUT - PD2/INT2/RXD1 RXEN1 PORTD2 * PUD RXEN1 0 0 0 INT2 ENABLE 1 INT2 INPUT/RXD1 - PD1/INT1/SDA TWEN PORTD1 * PUD TWEN SDA_OUT TWEN 0 INT1 ENABLE 1 INT1 INPUT SDA INPUT PD0/INT0/SCL TWEN PORTD0 * PUD TWEN SCL_OUT TWEN 0 INT0 ENABLE 1 INT0 INPUT SCL INPUT
1. When enabled, the Two-wire Serial Interface enables Slew-rate controls on the output pins PD0 and PD1. This is not shown on the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.
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Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 39. Table 39. Port E Pins Alternate Functions
Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Note: Alternate Function INT7/ICP3(1) (External Interrupt 7 Input or Timer/Counter3 Input Capture Pin) INT6/ T3(1) (External Interrupt 6 Input or Timer/Counter3 Clock Input) INT5/OC3C(1) (External Interrupt 5 Input or Output Compare and PWM Output C for Timer/Counter3) INT4/OC3B(1) (External Interrupt 4 Input or Output Compare and PWM Output B for Timer/Counter3) AIN1/OC3A (1) (Analog Comparator Negative Input or Output Compare and PWM Output A for Timer/Counter3) AIN0/XCK0(1) (Analog Comparator Positive Input or USART0 external clock input/output) PDO/TXD0 (Programming Data Output or UART0 Transmit Pin) PDI/RXD0 (Programming Data Input or UART0 Receive Pin) 1. ICP3, T3, OC3C, OC3B, OC3B, OC3A, and XCK0 not applicable in ATmega103 compatibility mode.
* INT7/ICP3 - Port E, Bit 7 INT7, External Interrupt Source 7: The PE7 pin can serve as an External Interrupt source. ICP3 - Input Capture Pin3: The PE7 pin can act as an Input Capture pin for Timer/Counter3. * INT6/T3 - Port E, Bit 6 INT6, External Interrupt Source 6: The PE6 pin can serve as an External Interrupt source. T3, Timer/Counter3 Counter Source. * INT5/OC3C - Port E, Bit 5 INT5, External Interrupt Source 5: The PE5 pin can serve as an External Interrupt source. OC3C, Output Compare Match C output: The PE5 pin can serve as an external output for the Timer/Counter3 Output Compare C. The pin has to be configured as an output (DDE5 set - one) to serve this function. The OC3C pin is also the output pin for the PWM mode timer function. * INT4/OC3B - Port E, Bit 4 INT4, External Interrupt Source 4: The PE4 pin can serve as an External Interrupt source. OC3B, Output Compare Match B output: The PE4 pin can serve as an external output for the Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDE4 set - one) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.
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* AIN1/OC3A - Port E, Bit 3 AIN1 - Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. OC3A, Output Compare Match A output: The PE3 pin can serve as an external output for the Timer/Counter3 Output Compare A. The pin has to be configured as an output (DDE3 set - one) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function. * AIN0/XCK0 - Port E, Bit 2 AIN0 - Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in synchronous mode. * PDO/TXD0 - Port E, Bit 1 PDO, SPI Serial Programming Data output. During Serial Program Downloading, this pin is used as data output line for the ATmega64. TXD0, UART0 Transmit Pin. * PDI/RXD0 - Port E, Bit 0 PDI, SPI Serial Programming Data input. During serial program downloading, this pin is used as data input line for the ATmega64. RXD0, USART0 Receive pin. Receive Data (Data Input pin for the USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up. Table 40 and Table 41 relates the alternate functions of Port E to the overriding signals shown in Figure 33 on page 71. Table 40. Overriding Signals for Alternate Functions PE7..PE4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PE7/INT7/ICP3 0 0 0 0 0 0 INT7 ENABLE 1 INT7 INPUT/ICP3 INPUT - PE6/INT6/T3 0 0 0 0 0 0 INT6 ENABLE 1 INT7 INPUT/T3 INPUT - PE5/INT5/OC3C 0 0 0 0 OC3C ENABLE OC3C INT5 ENABLE 1 INT5 INPUT - PE4/INT4/OC3B 0 0 0 0 OC3B ENABLE OC3B INT4 ENABLE 1 INT4 INPUT -
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Table 41. Overriding Signals for Alternate Functions in PE3..PE0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PE3/AIN1/OC3A 0 0 0 0 OC3B ENABLE OC3B 0 0 0 AIN1 INPUT PE2/AIN0/XCK0 0 0 0 0 UMSEL0 XCK0 OUTPUT 0 0 XCK0 INPUT AIN0 INPUT PE1/PDO/TXD0 TXEN0 0 TXEN0 1 TXEN0 TXD0 0 0 - - PE0/PDI/RXD0 RXEN0 PORTE0 * PUD RXEN0 0 0 0 0 0 RXD0 -
Alternate Functions of Port F
The Port F has an alternate function as analog input for the ADC as shown in Table 42. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. In ATmega103 compatibility mode Port F is input only. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs. Table 42. Port F Pins Alternate Functions
Port Pin PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Alternate Function ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test Clock) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0)
* TDI, ADC7 - Port F, Bit 7 ADC7, Analog to Digital Converter, Channel 7. TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. * TDO, ADC6 - Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. The TDO pin is tri-stated unless TAP states that shift out data are entered. 83
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* TMS, ADC5 - Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5. TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. * TCK, ADC4 - Port F, Bit 4 ADC4, Analog to Digital Converter, Channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. * ADC3 - ADC0 - Port F, Bit 3..0 Analog to Digital Converter, Channel 3..0. Table 43. Overriding Signals for Alternate Functions in PF7..PF4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PF7/ADC7/TDI JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TDI/ADC7 INPUT PF6/ADC6/TDO JTAGEN 0 JTAGEN SHIFT_IR + SHIFT_DR JTAGEN TDO JTAGEN 0 - ADC6 INPUT PF5/ADC5/TMS JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TMS/ADC5 INPUT PF4/ADC4/TCK JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TCKADC4 INPUT
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Table 44. Overriding Signals for Alternate Functions in PF3..PF0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PF3/ADC3 0 0 0 0 0 0 0 0 - ADC3 INPUT PF2/ADC2 0 0 0 0 0 0 0 0 - ADC2 INPUT PF1/ADC1 0 0 0 0 0 0 0 0 - ADC1 INPUT PF0/ADC0 0 0 0 0 0 0 0 0 - ADC0 INPUT
Alternate Functions of Port G
In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows: Table 45. Port G Pins Alternate Functions
Port Pin PG4 PG3 PG2 PG1 PG0 Alternate Function TOSC1 (RTC Oscillator Timer/Counter0) TOSC2 (RTC Oscillator Timer/Counter0) ALE (Address Latch Enable to external memory) RD (Read strobe to external memory) WR (Write strobe to external memory)
* TOSC1 - Port G, Bit 4 TOSC2, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. * TOSC2 - Port G, Bit 3 TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin cannot be used as an I/O pin. * ALE - Port G, Bit 2 ALE is the external data memory Address Latch Enable signal. * RD - Port G, Bit 1 RD is the external data memory read control strobe.
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* WR - Port G, Bit 0 WR is the external data memory write control strobe. Table 46 and Table 47 relates the alternate functions of Port G to the overriding signals shown in Figure 33 on page 71. Table 46. Overriding Signals for Alternate Functions in PG4..PG1
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PG4/TOSC1 AS0 0 AS0 0 0 0 AS0 0 - T/C0 OSC INPUT PG3/TOSC2 AS0 0 AS0 0 0 0 AS0 0 - T/C0 OSC OUTPUT PG2/ALE SRE 0 SRE 1 SRE ALE 0 0 - - PG1/RD SRE 0 SRE 1 SRE RD 0 0 - -
Table 47. Overriding Signals for Alternate Functions in PG0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PG0/WR SRE 0 SRE 1 SRE WR 0 0 - -
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Register Description for I/O Ports
PORTA - Port A Data Register
Bit 0x1B (0x3B) Read/Write Initial Value 7
PORTA7
6
PORTA6
5
PORTA5
4
PORTA4
3
PORTA3
2
PORTA2
1
PORTA1
0
PORTA0 PORTA
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DDRA - Port A Data Direction Register
Bit 0x1A (0x3A) Read/Write Initial Value
7 DDA7 R/W 0
6 DDA6 R/W 0
5 DDA5 R/W 0
4 DDA4 R/W 0
3 DDA3 R/W 0
2 DDA2 R/W 0
1 DDA1 R/W 0
0 DDA0 R/W 0 DDRA
PINA - Port A Input Pins Address
Bit 0x19 (0x39) Read/Write Initial Value
7 PINA7 R N/A
6 PINA6 R N/A
5 PINA5 R N/A
4 PINA4 R N/A
3 PINA3 R N/A
2 PINA2 R N/A
1 PINA1 R N/A
0 PINA0 R N/A PINA
PORTB - Port B Data Register
Bit 0x18 (0x38) Read/Write Initial Value 7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DDRB - Port B Data Direction Register
Bit 0x17 (0x37) Read/Write Initial Value
7 DDB7 R/W 0
6 DDB6 R/W 0
5 DDB5 R/W 0
4 DDB4 R/W 0
3 DDB3 R/W 0
2 DDB2 R/W 0
1 DDB1 R/W 0
0 DDB0 R/W 0 DDRB
PINB - Port B Input Pins Address
Bit 0x16 (0x36) Read/Write Initial Value
7 PINB7 R N/A
6 PINB6 R N/A
5 PINB5 R N/A
4 PINB4 R N/A
3 PINB3 R N/A
2 PINB2 R N/A
1 PINB1 R N/A
0 PINB0 R N/A PINB
PORTC - Port C Data Register
Bit 0x15 (0x35) Read/Write Initial Value 7
PORTC7
6
PORTC6
5
PORTC5
4
PORTC4
3
PORTC3
2
PORTC2
1
PORTC1
0
PORTC0 PORTC
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DDRC - Port C Data Direction Register
Bit 0x14 (0x34) Read/Write Initial Value
7 DDC7 R/W 0
6 DDC6 R/W 0
5 DDC5 R/W 0
4 DDC4 R/W 0
3 DDC3 R/W 0
2 DDC2 R/W 0
1 DDC1 R/W 0
0 DDC0 R/W 0 DDRC
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PINC - Port C Input Pins Address
Bit 0x13 (0x33) Read/Write Initial Value
7 PINC7 R N/A
6 PINC6 R N/A
5 PINC5 R N/A
4 PINC4 R N/A
3 PINC3 R N/A
2 PINC2 R N/A
1 PINC1 R N/A
0 PINC0 R N/A PINC
In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-pull Zero Output. The port pins assumes their Initial Value, even if the clock is not running. Note that the DDRC and PINC registers are available in ATmega103 compatibility mode, and should not be used for 100% backward compatibility. PORTD - Port D Data Register
Bit 0x12 (0x32) Read/Write Initial Value 7
PORTD7
6
PORTD6
5
PORTD5
4
PORTD4
3
PORTD3
2
PORTD2
1
PORTD1
0
PORTD0 PORTD
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DDRD - Port D Data Direction Register
Bit 0x11 (0x31) Read/Write Initial Value
7 DDD7 R/W 0
6 DDD6 R/W 0
5 DDD5 R/W 0
4 DDD4 R/W 0
3 DDD3 R/W 0
2 DDD2 R/W 0
1 DDD1 R/W 0
0 DDD0 R/W 0 DDRD
PIND - Port D Input Pins Address
Bit 0x10 (0x30) Read/Write Initial Value
7 PIND7 R N/A
6 PIND6 R N/A
5 PIND5 R N/A
4 PIND4 R N/A
3 PIND3 R N/A
2 PIND2 R N/A
1 PIND1 R N/A
0 PIND0 R N/A PIND
PORTE - Port E Data Register
Bit 0x03 (0x23) Read/Write Initial Value 7
PORTE7
6
PORTE6
5
PORTE5
4
PORTE4
3
PORTE3
2
PORTE2
1
PORTE1
0
PORTE0 PORTE
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DDRE - Port E Data Direction Register
Bit 0x02 (0x22) Read/Write Initial Value
7 DDE7 R/W 0
6 DDE6 R/W 0
5 DDE5 R/W 0
4 DDE4 R/W 0
3 DDE3 R/W 0
2 DDE2 R/W 0
1 DDE1 R/W 0
0 DDE0 R/W 0 DDRE
PINE - Port E Input Pins Address
Bit 0x01 (0x21) Read/Write Initial Value
7 PINE7 R N/A
6 PINE6 R N/A
5 PINE5 R N/A
4 PINE4 R N/A
3 PINE3 R N/A
2 PINE2 R N/A
1 PINE1 R N/A
0 PINE0 R N/A PINF
PORTF - Port F Data Register
Bit (0x62) Read/Write Initial Value 7
PORTF7
6
PORTF6
5
PORTF5
4
PORTF4
3
PORTF3
2
PORTF2
1
PORTF1
0
PORTF0 PORTF
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
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DDRF - Port F Data Direction Register
Bit (0x61) Read/Write Initial Value 7 DDF7 R/W 0 6 DDF6 R/W 0 5 DDF5 R/W 0 4 DDF4 R/W 0 3 DDF3 R/W 0 2 DDF2 R/W 0 1 DDF1 R/W 0 0 DDF0 R/W 0 DDRF
PINF - Port F Input Pins Address
Bit 0x00 (0x20) Read/Write Initial Value
7 PINF7 R N/A
6 PINF6 R N/A
5 PINF5 R N/A
4 PINF4 R N/A
3 PINF3 R N/A
2 PINF2 R N/A
1 PINF1 R N/A
0 PINF0 R N/A PINF
Note that PORTF and DDRF Registers are not available in ATmega103 compatibility mode where Port F serves as digital input only. PORTG - Port G Data Register
Bit (0x65) Read/Write Initial Value 7
-
6
-
5
-
4
PORTG4
3
PORTG3
2
PORTG2
1
PORTG1
0
PORTG0 PORTG
R 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DDRG - Port G Data Direction Register
Bit (0x64) Read/Write Initial Value
7 - R 0
6 - R 0
5 - R 0
4 DDG4 R/W 0
3 DDG3 R/W 0
2 DDG2 R/W 0
1 DDG1 R/W 0
0 DDG0 R/W 0 DDRG
PING - Port G Input Pins Address
Bit (0x63) Read/Write Initial Value
7 - R 0
6 - R 0
5 - R 0
4 PING4 R N/A
3 PING3 R N/A
2 PING2 R N/A
1 PING1 R N/A
0 PING0 R N/A PING
Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility mode. In the ATmega103 compatibility mode Port G serves its alternate functions only (TOSC1, TOSC2, WR, RD and ALE).
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External Interrupts
The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the External Interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in "Clock Systems and their Distribution" on page 37. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V and 25C. The frequency of the Watchdog Oscillator is voltage dependent as shown in the "Electrical Characteristics" on page 327. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT Fuses as described in "Clock Systems and their Distribution" on page 37. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt.
EICRA - External Interrupt Control Register A
Bit (0x6A) Read/Write Initial Value
7 ISC31 R/W 0
6 ISC30 R/W 0
5 ISC21 R/W 0
4 ISC20 R/W 0
3 ISC11 R/W 0
2 ISC10 R/W 0
1 ISC01 R/W 0
0 ISC00 R/W 0 EICRA
This Register can not be reached in ATmega103 compatibility mode, but the Initial Value defines INT3:0 as low level interrupts, as in ATmega103. * Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 48. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 49 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is reenabled.
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Table 48. Interrupt Sense Control(1)
ISCn1 0 0 1 1 Note: ISCn0 0 1 0 1 Description The low level of INTn generates an interrupt request. Reserved The falling edge of INTn generates asynchronously an interrupt request. The rising edge of INTn generates asynchronously an interrupt request.
1. n = 3, 2, 1or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Table 49. Asynchronous External Interrupt Characteristics
Symbol tINT Parameter Minimum pulse width for asynchronous External Interrupt Condition Min Typ 50 Max Units ns
EICRB - External Interrupt Control Register B
Bit 0x3A (0x5A) Read/Write Initial Value
7 ISC71 R/W 0
6 ISC70 R/W 0
5 ISC61 R/W 0
4 ISC60 R/W 0
3 ISC51 R/W 0
2 ISC50 R/W 0
1 ISC41 R/W 0
0 ISC40 R/W 0 EICRB
* Bits 7..0 - ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 50. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 50. Interrupt Sense Control(1)
ISCn1 0 0 1 1 Note: ISCn0 0 1 0 1 Description The low level of INTn generates an interrupt request. Any logical change on INTn generates an interrupt request The falling edge between two samples of INTn generates an interrupt request. The rising edge between two samples of INTn generates an interrupt request.
1. n = 7, 6, 5 or 4. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
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EIMSK - External Interrupt Mask Register
Bit 0x39 (0x59) Read/Write Initial Value
7 INT7 R/W 0
6 INT6 R/W 0
5 INT5 R/W 0
4 INT4 R/W 0
3 INT3 R/W 0
2 INT2 R/W 0
1 INT1 R/W 0
0 INT0 R/W 0 EIMSK
* Bits 7..4 - INT7 - INT0: External Interrupt Request 7 - 0 Enable When an INT7 - INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers - EICRA and EICRB defines whether the External Interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. EIFR - External Interrupt Flag Register
Bit 0x38 (0x58) Read/Write Initial Value
7 INTF7 R/W 0
6 INTF6 R/W 0
5 INTF5 R/W 0
4 INTF4 R/W 0
3 INTF3 R/W 0
2 INTF2 R/W 0
1 INTF1 R/W 0
0 INTF0 R/W 0 EIFR
* Bits 7..0 - INTF7 - INTF0: External Interrupt Flags 7 - 0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding Interrupt Enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See "Digital Input Enable and Sleep Modes" on page 70 for more information.
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8-bit Timer/Counter0 with PWM and Asynchronous Operation
Timer/Counter0 is a general purpose, single-channel, 8-bit Timer/Counter module. The main features are: * Single Channel Counter * Clear Timer on Compare Match (Auto Reload) * Glitch-free, Phase Correct Pulse Width Modulator (PWM) * Frequency Generator * 10-bit Clock Prescaler * Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) * Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 34. For the actual placement of I/O pins, refer to "Pin Configuration" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "8-bit Timer/Counter Register Description" on page 104. Figure 34. 8-bit Timer/Counter Block Diagram
TCCRn
Overview
count clear direction Control Logic
TOVn (Int. Req.) clkTn TOSC1
BOTTOM
TOP Prescaler
T/C Oscillator TOSC2
Timer/Counter TCNTn
=0
= 0xFF
OCn (Int. Req.) clkI/O
=
Waveform Generation
OCn
OCRn
DATABUS
Synchronized Status Flags
clkI/O Synchronization Unit clkASY
Status Flags
ASSRn Asynchronous Mode Select (ASn)
Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous
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operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0). See "Output Compare Unit" on page 95. for details. The Compare Match event will also set the Compare Flag (OCF0) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this datasheet are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used i.e. TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 51 are also used extensively throughout this section. Table 51. Definitions BOTTOM MAX TOP The counter reaches the BOTTOM when it becomes zero (0x00). The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation.
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT0 is by default equal to the MCU clock, clkI/O. When the AS0 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see "ASSR - Asynchronous Status Register" on page 107. For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 110.
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Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 35 shows a block diagram of the counter and its surrounding environment. Figure 35. Counter Unit Block Diagram
DATA BUS
TOVn (Int.Req.)
TOSC1 count TCNTn clear direction Control Logic clk Tn Prescaler T/C Oscillator TOSC2
bottom
top
clkI/O
Signal description (internal signals): count direction clear clkT0 top bottom Increment or decrement TCNT0 by 1. Selects between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock. Signalizes that TCNT0 has reached maximum value. Signalizes that TCNT0 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 98. The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF0 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0 flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation ("Modes of Operation" on page 98). Figure 36 shows a block diagram of the Output Compare unit.
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Figure 36. Output Compare Unit, Block Diagram
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top bottom FOCn
Waveform Generator
OCxy
WGMn1:0
COMn1:0
The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled the CPU will access the OCR0 directly. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0) bit. Forcing Compare Match will not set the OCF0 flag or reload/clear the timer, but the OC0 pin will be updated as if a real Compare Match had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or toggled). All CPU write operations to the TCNT0 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare (FOC0) strobe bit in Normal mode. The OC0 Register keeps its value even when changing between waveform generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately.
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
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Compare Match Output Unit
The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 37 shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the reference is for the internal OC0 Register, not the OC0 pin. Figure 37. Compare Match Output Unit, Schematic
COMn1 COMn0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCn D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0) from the Waveform Generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0 state before the output is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. See "8-bit Timer/Counter Register Description" on page 104. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM01:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no action on the OC0 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 53 on page 105. For fast PWM mode, refer to Table 54 on page 105, and for phase correct PWM refer to Table 55 on page 105.
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A change of the COM01:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits.
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See "Compare Match Output Unit" on page 97.). For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 102.
Normal Mode
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 38. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared. Figure 38. CTC Mode, Timing Diagram
OCn Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMn1:0 = 1)
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An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCn = ---------------------------------------------2 N ( 1 + OCRn ) The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dualslope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 39. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0 and TCNT0.
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Figure 39. Fast PWM Mode, Timing Diagram
OCRn Interrupt Flag Set
OCRn Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM01:0 to three (See Table 54 on page 105). The actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0 Register at the Compare Match between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnPWM = ----------------N 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0 to toggle its logical level on each Compare Match (COM01:0 = 1). The waveform generated will have a maximum frequency of foc0 = fclk_I/O/2 when OCR0 is set to zero. This feature is similar to the OC0 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
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Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 40. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0 and TCNT0. Figure 40. Phase Correct PWM Mode, Timing Diagram
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM01:0 to three (See Table 55 on page 105). The actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0 Register at the Compare Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at Compare Match
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between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 40 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. * OCR0 changes its value from MAX, like in Figure 40. When the OCR0 value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. The timer starts counting from a higher value than the one in OCR0, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up.
*
Timer/Counter Timing Diagrams
Figure 41 and Figure 42 contain timing data for the Timer/Counter operation. The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal. The figure shows the count sequence close to the MAX value. Figure 43 and Figure 44 show the same timing data, but with the prescaler enabled. The figures illustrate when interrupt flags are set. The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT0) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are set. Figure 41 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 41. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 42 shows the same timing data, but with the prescaler enabled.
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Figure 42. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
Figure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 44. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
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8-bit Timer/Counter Register Description
TCCR0 - Timer/Counter Control Register
Bit 0x33 (0x53) Read/Write Initial Value 7 FOC0 W 0 6 WGM00 R/W 0 5 COM01 R/W 0 4 COM00 R/W 0 3 WGM01 R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0
* Bit 7 - FOC0: Force Output Compare The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate Compare Match is forced on the waveform generation unit. The OC0 output is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. * Bit 6, 3 - WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 52 and "Modes of Operation" on page 98. Table 52. Waveform Generation Mode Bit Description(1)
Mode 0 1 2 3 Note: WGM01 (CTC0) 0 0 1 1 WGM00 (PWM0) 0 1 0 1 Timer/Counter Mode of Operation Normal PWM, Phase Correct CTC Fast PWM TOP 0xFF 0xFF OCR0 0xFF Update of OCR0 at Immediate TOP Immediate BOTTOM TOV0 Flag Set on MAX BOTTOM MAX MAX
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.
* Bit 5:4 - COM01:0: Compare Match Output Mode These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 53 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a Normal or CTC mode (non-PWM).
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Table 53. Compare Output Mode, non-PWM Mode
COM01 0 0 1 1 COM00 0 1 0 1 Description Normal port operation, OC0 disconnected. Toggle OC0 on Compare Match. Clear OC0 on Compare Match. Set OC0 on Compare Match.
Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 54. Compare Output Mode, Fast PWM Mode(1)
COM01 0 0 1 1 COM00 0 1 0 1 Description Normal port operation, OC0 disconnected. Reserved Clear OC0 on Compare Match, set OC0 at BOTTOM, (non-inverting mode). Set OC0 on Compare Match, clear OC0 at BOTTOM, (inverting mode).
Note:
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM Mode" on page 99 for more details.
Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Table 55. Compare Output Mode, Phase Correct PWM Mode(1)
COM01 0 0 1 1 Note: COM00 0 1 0 1 Description Normal port operation, OC0 disconnected. Reserved. Clear OC0 on Compare Match when up-counting. Set OC0 on Compare Match when downcounting. Set OC0 on Compare Match when up-counting. Clear OC0 on Compare Match when downcounting.
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 101 for more details.
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* Bit 2:0 - CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 56. Table 56. Clock Select Bit Description
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description No clock source (Timer/counter stopped) clkT0S/(No prescaling) clkT0S/8 (From prescaler) clkT0S/32 (From prescaler) clkT0S/64 (From prescaler) clkT0S/128 (From prescaler) clkT0S/256 (From prescaler) clkT0S/1024 (From prescaler)
TCNT0 - Timer/Counter Register
Bit 0x32 (0x52) Read/Write Initial Value
7
6
5
4
3
2
1
0 TCNT0
TCNT0[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0 Register. OCR0 - Output Compare Register
Bit 0x31 (0x51) Read/Write Initial Value
7
6
5
4
3
2
1
0 OCR0
OCR0[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0 pin.
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Asynchronous Operation of the Timer/Counter
ASSR - Asynchronous Status Register
Bit 0x30 (0x50) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 AS0 R/W 0 2 TCN0UB R 0 1 OCR0UB R 0 0 TCR0UB R 0 ASSR
* Bit 3 - AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O. When AS0 is written to one, Timer/Counter 0 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and TCCR0 might be corrupted. * Bit 2 - TCN0UB: Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value. * Bit 1 - OCR0UB: Output Compare Register0 Update Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set. When OCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value. * Bit 0 - TCR0UB: Timer/Counter Control Register0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set. When TCCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is read. Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates asynchronously, some considerations must be taken. * Warning: When switching between asynchronous and synchronous clocking of Timer/Counter0, the timer registers TCNT0, OCR0, and TCCR0 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0. 2. Select clock source by setting AS0 as appropriate. 3. Write new values to TCNT0, OCR0, and TCCR0. 4. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB. 5. Clear the Timer/Counter0 interrupt flags.
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6. Enable interrupts, if needed. * The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, for example, writing to TCNT0 does not disturb an OCR0 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented. When entering Power-save or Extended Standby mode after having written to TCNT0, OCR0, or TCCR0, the user must wait until the written register has been updated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare0 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR0 or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the OCR0UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up. If Timer/Counter0 is used to wake the device up from Power-save or Extended Standby mode, precautions must be taken if the user wants to reenter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR0, TCNT0, or OCR0. 2. Wait until the corresponding Update Busy flag in ASSR returns to zero. 3. Enter Power-save or Extended Standby mode. * When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter0 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter0 after Power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter0 registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. Reading of the TCNT0 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT0 is clocked on the asynchronous TOSC clock, reading TCNT0 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT0 will
*
*
*
*
*
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read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as follows: 1. Write any value to either of the registers OCR0 or TCCR0. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT0. * During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock.
TIMSK - Timer/Counter Interrupt Mask Register
Bit 0x37 (0x57) Read/Write Initial Value
7
OCIE2
6
TOIE2
5
TICIE1
4
OCIE1A
3
OCIE1B
2
TOIE1
1
OCIE0
0
TOIE0 TIMSK
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 1 - OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. TIFR - Timer/Counter Interrupt Flag Register
Bit 0x36 (0x56) Read/Write Initial Value
7 OCF2 R/W 0
6 TOV2 R/W 0
5 ICF1 R/W 0
4 OCF1A R/W 0
3 OCF1B R/W 0
2 TOV1 R/W 0
1 OCF0 R/W 0
0 TOV0 R/W 0 TIFR
* Bit 1 - OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.
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* Bit 0 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00.
Timer/Counter Prescaler
Figure 45. Prescaler for Timer/Counter0
clkOSC TOSC1
clkT0S Clear
10-BIT T/C PRESCALER
clkT0S/32
clkT0S/64
AS0
PSR0
0
CS00 CS01 CS02
TIMER/COUNTER0 CLOCK SOURCE clkT0
The clock source for Timer/Counter0 is named clkT0S. clkT0S is by default connected to the main system clock clkOSC. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). When AS0 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter0. The Oscillator is optimized for use with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clkT0S/32, clkT0S/64, clkT0S/128, clkT0S/256, and clkT0S/1024. Additionally, clkT0S as well as 0 (stop) may be selected. Setting the PSR0 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler.
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clkT0S/1024
clkT0S/8
clkT0S/128
clkT0S/256
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SFIOR - Special Function IO Register
Bit 0x20 (0x40) Read/Write Initial Value 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR0 R/W 0 0 PSR321 R/W 0 SFIOR
* Bit 7 - TSM: Timer/Counter Synchronization Mode Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit written zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. * Bit 1 - PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. The bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set.
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16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: * True 16-bit Design (i.e., Allows 16-bit PWM) * Three Independent Output Compare Units * Double Buffered Output Compare Registers * One Input Capture Unit * Input Capture Noise Canceler * Clear Timer on Compare Match (Auto Reload) * Glitch-free, Phase Correct Pulse Width Modulator (PWM) * Variable PWM Period * Frequency Generator * External Event Counter * Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A,
OCF3B, OCF3C, and ICF3)
Restrictions in ATmega103 Compatibility Mode
Note that in ATmega103 compatibility mode, only one 16-bit Timer/Counter is available (Timer/Counter1). Also note that in ATmega103 compatibility mode, the Timer/Counter1 has two compare registers (Compare A and Compare B) only. Most register and bit references in this datasheet are written in general form. A lower case "n" replaces the Timer/Counter number, and a lower case "x" replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used (i.e,. TCNT1 for accessing Timer/Counter1 counter value and so on). The physical I/O Register and bit locations for ATmega64 are listed in the "16-bit Timer/Counter Register Description" on page 133. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
Overview
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Figure 46. 16-bit Timer/Counter Block Diagram(1)
Count Clear Direction Control Logic TOVx (Int.Req.) TCLK Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTx Tx
=
=0
OCFxA (Int.Req.)
=
OCRxA Fixed TOP Values
Waveform Generation
OCxA
OCFxB (Int.Req.) Waveform Generation OCxB
=
DATA BUS
OCRxB
OCFxC (Int.Req.)
=
OCRxC ICFx (Int.Req.) Edge Detector
Waveform Generation
OCxC
( From Analog Comparator Ouput )
ICRx
Noise Canceler ICPx
TCCRxA
TCCRxB
TCCRxC
Note:
1. Refer to Figure 1 on page 2, Table 30 on page 74, and Table 39 on page 81 for Timer/Counter1 and 3 pin placement and description.
Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section "Accessing 16-bit Registers" on page 115. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR) and Extended Timer Interrupt Flag Register (ETIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK) and Extended Timer Interrupt Mask Register (ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkTn).
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The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare Pin (OCnA/B/C). See "Output Compare Units" on page 121. The Compare Match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See "Analog Comparator" on page 228.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used as an alternative, freeing the OCRnA to be used as PWM output. Definitions The following definitions are used extensively throughout this section: Table 57. Definitions BOTTOM MAX TOP The counter reaches the BOTTOM when it becomes 0x0000. The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation.
Compatibility
The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: * * * All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. Bit locations inside all 16-bit Timer/Counter registers, including Timer Interrupt Registers. Interrupt Vectors.
The following control bits have changed name, but have same functionality and register location: * * * * * * 114 PWMn0 is changed to WGMn0. PWMn1 is changed to WGMn1. CTCn is changed to WGMn2. Timer/Counter Control Register C (TCCRnC). Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC. COM1C1:0 are added to TCCR1A.
The following registers are added to the 16-bit Timer/Counter:
The following bits are added to the 16-bit Timer/Counter control registers:
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* * FOCnA, FOCnB, and FOCnC are added in the new TCCRnC Register. WGMn3 is added to TCCRnB.
Interrupt flag and mask bits for Output Compare unit C are added. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases.
Accessing 16-bit Registers
The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnA/B/C 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnA/B/C and ICRn Registers. Note that when using "C", the compiler handles the 16-bit access. Assembly Code Examples(1)
... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in in ... r16,TCNTnL r17,TCNTnH
C Code Examples(1)
unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ...
Note:
1. See "About Code Examples" on page 9.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
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It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example(1)
TIM16_ReadTCNTn: ; Save global interrupt flag in cli ; Read TCNTn into r17:r16 in in r16,TCNTnL r17,TCNTnH r18,SREG ; Disable interrupts
; Restore global interrupt flag out SREG,r18 ret
C Code Example(1)
unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; }
Note:
1. See "About Code Examples" on page 9. The assembly code example returns the TCNTn value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example(1)
TIM16_WriteTCNTn: ; Save global interrupt flag in cli ; Set TCNTn to r17:r16 out TCNTnH,r17 out TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret r18,SREG ; Disable interrupts
C Code Example(1)
void TIM16_WriteTCNTn( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; }
Note:
1. See "About Code Examples" on page 9. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn.
Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler, see "Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers" on page 144. The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 47 shows a block diagram of the counter and its surroundings.
Timer/Counter Clock Sources
Counter Unit
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Figure 47. Counter Unit Block Diagram
DATA BUS
(8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction Control Logic clkTn Edge Detector Tn
TCNTn (16-bit Counter)
( From Prescaler ) TOP BOTTOM
Signal description (internal signals): Count Direction Clear clkTn TOP BOTTOM Increment or decrement TCNTn by 1. Select between increment and decrement. Clear TCNTn (set all bits to zero). Timer/counter clock. Signalize that TCNTn has reached maximum value. Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each Timer Clock (clkTn). The clkTn can be generated from an external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 124. The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
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Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 48. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small "n" in register and bit names indicates the Timer/Counter number. Figure 48. Input Capture Unit Block Diagram(1)
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACO* Analog Comparator ICPn
ACIC*
ICNC
ICES
Noise Canceler
Edge Detector
ICFn (Int.Req.)
Note:
1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP - not Timer/Counter3.
When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn = 1), the Input Capture Flag generates an Input Capture interrupt. The ICFn flag is automatically cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter's TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be
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written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 115. Input Capture Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the Tn pin (Figure 59 on page 144). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to define TOP. An Input Capture can be triggered by software by controlling the port of the ICPn pin. Noise Canceler The Noise Canceler improves noise immunity by using a simple digital filtering scheme. The Noise Canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The Noise Canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control Register B (TCCRnB). When enabled the Noise Canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICRn Register. The Noise Canceler uses the system clock and is therefore not affected by the prescaler. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used).
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Output Compare Units
The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare interrupt. The OCFnx flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See "Modes of Operation" on page 124.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 49 shows a block diagram of the Output Compare unit. The small "n" in the register and bit names indicates the device number (n = n for Timer/Counter n), and the "x" indicates Output Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 49. Output Compare Unit, Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.) TOP BOTTOM
Waveform Generator
OCnx
WGMn3:0
COMnx1:0
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double
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buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNTn - and ICRn Register). Therefore OCRnx is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCRnx registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper eight bits of either the OCRnx Buffer or OCRnx Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 115. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare Match will not set the OCFnx flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare Match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or toggled). All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. Since writing TCNTn in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNTn when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when changing between waveform generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately.
Compare Match Blocking by TCNTn Write
Using the Output Compare Unit
Compare Match Output Unit
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next Compare Match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 50 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a System Reset occur, the OCnx Register is reset to "0".
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Figure 50. Compare Match Output Unit, Schematic
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 58, Table 59 and Table 60 for details. The design of the Output Compare pin logic allows initialization of the OCnx state before the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See "16-bit Timer/Counter Register Description" on page 133. The COMnx1:0 bits have no effect on the Input Capture unit. Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 58 on page 134. For fast PWM mode refer to Table 59 on page 134, and for phase correct and phase and frequency correct PWM refer to Table 60 on page 135. A change of the COMnx1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits.
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Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a Compare Match (See "Compare Match Output Unit" on page 122.) For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 131.
Normal Mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOVn flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 51. The counter value (TCNTn) increases until a Compare Match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared.
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Figure 51. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnA (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is defined by the following equation: f clk_I/O f OCnA = -------------------------------------------------2 N ( 1 + OCRnA ) The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOVn flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx, and set at BOTTOM. In inverting Compare Output mode output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High
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frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R FPWM = ---------------------------------log ( 2 ) In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 52. The figure shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent Compare Matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a Compare Match occurs. Figure 52. Fast PWM Mode, Timing Diagram
OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is
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changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the buffer register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 59 on page 134). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ---------------------------------N ( 1 + TOP ) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COMnx1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnA to toggle its logical level on each Compare Match (COMnA1:0 = 1). This applies only if OCRnA is used to define the TOP value (WGMn3:0 = 15). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. 127
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The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: R PCPWM = log ( TOP + 1 ) ---------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 53. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent Compare Matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a Compare Match occurs. Figure 53. Phase Correct PWM Mode, Timing Diagram
OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set accordingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 53 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs
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at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 60 on page 135). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx while upcounting, and set on the Compare Match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dualslope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 53 and Figure 54). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ---------------------------------log ( 2 )
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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 54. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent Compare Matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a Compare Match occurs. Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag set when TCNTn has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNTn and the OCRnx. As Figure 54 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCRnx registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a
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non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 60 on page 135). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f clk_I/O f OCnxPFCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle.
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCFnx. Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 56 shows the same timing data, but with the prescaler enabled.
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Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 57 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at BOTTOM. Figure 57. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 58 shows the same timing data, but with the prescaler enabled.
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Figure 58. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
16-bit Timer/Counter Register Description
TCCR1A -Timer/Counter1 Control Register A
Bit 0x2F (0x4F) Read/Write Initial Value 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
COM1C1
2
COM1C0
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
TCCR3A - Timer/Counter3 Control Register A
Bit (0x8B) Read/Write Initial Value
7
COM3A1
6
COM3A0
5
COM3B1
4
COM3B0
3
COM3C1
2
COM3C0
1
WGM31
0
WGM30 TCCR3A
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7:6 - COMnA1:0: Compare Output Mode for Channel A * Bit 5:4 - COMnB1:0: Compare Output Mode for Channel B * Bit 3:2 - COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0, and COMnC1:0 control the Output Compare pins (OCnA, OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 58 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
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Table 58. Compare Output Mode, non-PWM
COMnA1/ COMnB1/ COMnC1 0 0 1 1 COMnA0/ COMnB0/ COMnC0 0 1 0 1
Description Normal port operation, OCnA/OCnB/OCnC disconnected. Toggle OCnA/OCnB/OCnC on Compare Match. Clear OCnA/OCnB/OCnC on Compare Match (Set output to low level). Set OCnA/OCnB/OCnC on Compare Match (Set output to high level).
Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode Table 59. Compare Output Mode, Fast PWM(1)
COMnA1/ COMnB1/ COMnC0 0 0 COMnA0/ COMnB0/ COMnC0 0 1
Description Normal port operation, OCnA/OCnB/OCnC disconnected. WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB/OCnC disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB/OCnC disconnected. Clear OCnA/OCnB/OCnC on Compare Match, set OCnA/OCnB/OCnC at BOTTOM (non-inverting mode). Set OCnA/OCnB/OCnC on Compare Match, clear OCnA/OCnB/OCnC at BOTTOM (inverting mode).
1 1 Note:
0 1
1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1/COMnC1 is set. In this case the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM Mode" on page 125. for more details.
Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct and frequency correct PWM mode.
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Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COMnA1/ COMnB1/ COMnC1 0 0 COMnA0/ COMnB0/ COMnC0 0 1
Description Normal port operation, OCnA/OCnB/OCnC disconnected. WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB/OCnC disconnected (normal port operation). Forr all other WGMn settings, normal port operation, OCnA/OCnB/OCnC disconnected. Clear OCnA/OCnB/OCnC on Compare Match when upcounting. Set OCnA/OCnB/OCnC on Compare Match when downcounting. Set OCnA/OCnB/OCnC on Compare Match when up-counting. Clear OCnA/OCnB/OCnC on Compare Match when downcounting.
1
0
1
1
Note:
1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1/COMnC1 is set. See "Phase Correct PWM Mode" on page 127. for more details.
* Bit 1:0 - WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 61. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See "Modes of Operation" on page 124.)
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Table 61. Waveform Generation Mode Bit Description
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGMn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WGMn2 (CTCn) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGMn1 (PWMn1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGMn0 (PWMn0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Timer/Counter Mode of Operation Normal PWM, Phase Correct, 8-bit PWM, Phase Correct, 9-bit PWM, Phase Correct, 10-bit CTC Fast PWM, 8-bit Fast PWM, 9-bit Fast PWM, 10-bit PWM, Phase and Frequency Correct PWM, Phase and Frequency Correct PWM, Phase Correct PWM, Phase Correct CTC (Reserved) Fast PWM Fast PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCRnA 0x00FF 0x01FF 0x03FF ICRn OCRnA ICRn OCRnA ICRn - ICRn OCRnA Update of OCRnx at Immediate TOP TOP TOP Immediate BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM TOP TOP Immediate - BOTTOM BOTTOM TOVn Flag Set on MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.
TCCR1B - Timer/Counter1 Control Register B
Bit 0x2E (0x4E) Read/Write Initial Value
7 ICNC1 R/W 0
6 ICES1 R/W 0
5 - R 0
4 WGM13 R/W 0
3 WGM12 R/W 0
2 CS12 R/W 0
1 CS11 R/W 0
0 CS10 R/W 0 TCCR1B
TCCR3B - Timer/Counter3 Control Register B
Bit (0x8A) Read/Write Initial Value
7 ICNC3 R/W 0
6 ICES3 R/W 0
5 - R 0
4 WGM33 R/W 0
3 WGM32 R/W 0
2 CS32 R/W 0
1 CS31 R/W 0
0 CS30 R/W 0 TCCR3B
* Bit 7 - ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.
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* Bit 6 - ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. * Bit 5 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. * Bit 4:3 - WGMn3:2: Waveform Generation Mode See TCCRnA Register description. * Bit 2:0 - CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 55 and Figure 56. Table 62. Clock Select Bit Description
CSn2 0 0 0 0 1 1 1 1 CSn1 0 0 1 1 0 0 1 1 CSn0 0 1 0 1 0 1 0 1 Description No clock source (Timer/counter stopped). clkI/O/1 (No prescaling) clkI/O/8 (From prescaler) clkI/O/64 (From prescaler) clkI/O/256 (From prescaler) clkI/O/1024 (From prescaler) External clock source on Tn pin. Clock on falling edge. External clock source on Tn pin. Clock on rising edge.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. TCCR1C - Timer/Counter1 Control Register C
Bit (0x7A) Read/Write Initial Value
7 FOC1A W 0
6 FOC1B W 0
5 FOC1C W 0
4 - R 0
3 - R 0
2 - R 0
1 - R 0
0 - R 0 TCCR1C
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TCCR3C - Timer/Counter3 Control Register C
Bit (0x8C) Read/Write Initial Value
7 FOC3A W 0
6 FOC3B W 0
5 FOC3C W 0
4 - R 0
3 - R 0
2 - R 0
1 - R 0
0 - R 0 TCCR3C
* Bit 7 - FOCnA: Force Output Compare for Channel A * Bit 6 - FOCnB: Force Output Compare for Channel B * Bit 5 - FOCnC: Force Output Compare for Channel C The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate Compare Match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB/FOCnB bits are always read as zero. * Bit 4:0 - Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when TCCRnC is written. TCNT1H and TCNT1L - Timer/Counter1
Bit 0x2D (0x4D) 0x2C (0x4C) Read/Write Initial Value
7
6
5
4
3
2
1
0 TCNT1H TCNT1L
TCNT1[15:8] TCNT1[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNT3H and TCNT3L - Timer/Counter3
Bit (0x89) (0x88) Read/Write Initial Value
7
6
5
4
3
2
1
0 TCNT3H TCNT3L
TCNT3[15:8] TCNT3[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 115. Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a Compare Match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the Compare Match on the following timer clock for all compare units.
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OCR1AH and OCR1AL - Output Compare Register 1 A
Bit 0x2B (0x4B) 0x2A (0x4A) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0
OCR1A[15:8] OCR1A[7:0] R/W 0 R/W 0
OCR1BH and OCR1BL - Output Compare Register 1 B
Bit 0x29 (0x49) 0x28 (0x48) Read/Write Initial Value
7
6
5
4
3
2
1
0 OCR1BH OCR1BL
OCR1B[15:8] OCR1B[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
OCR1CH and OCR1CL - Output Compare Register 1 C
Bit (0x79) (0x78) Read/Write Initial Value
7
6
5
4
3
2
1
0 OCR1CH OCR1CL
OCR1C[15:8] OCR1C[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
OCR3AH and OCR3AL - Output Compare Register 3 A
Bit (0x87) (0x86) Read/Write Initial Value
7
6
5
4
3
2
1
0 OCR3AH OCR3AL
OCR3A[15:8] OCR3A[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
OCR3BH and OCR3BL - Output Compare Register 3 B
Bit (0x85) (0x84) Read/Write Initial Value
7
6
5
4
3
2
1
0 OCR3BH OCR3BL
OCR3B[15:8] OCR3B[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
OCR3CH and OCR3CL - Output Compare Register 3 C
Bit (0x83) (0x82) Read/Write Initial Value
7
6
5
4
3
2
1
0 OCR3CH OCR3CL
OCR3C[15:8] OCR3C[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 115.
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ICR1H and ICR1L - Input Capture Register 1
Bit 0x27 (0x47) 0x26 (0x46) Read/Write Initial Value
7
6
5
4
3
2
1
0 ICR1H ICR1L
ICR1[15:8] ICR1[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
ICR3H and ICR3L - Input Capture Register 3
Bit (0x81) (0x80) Read/Write Initial Value
7
6
5
4
3
2
1
0 ICR3H ICR3L
ICR3[15:8] ICR3[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 115. TIMSK - Timer/Counter Interrupt Mask Register(1)
Bit 0x37 (0x57) Read/Write Initial Value
7 OCIE2 R/W 0
6 TOIE2 R/W 0
5 TICIE1 R/W 0
4 OCIE1A R/W 0
3 OCIE1B R/W 0
2 TOIE1 R/W 0
1 OCIE0 R/W 0
0 TOIE0 R/W 0 TIMSK
Note:
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
* Bit 5 - TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the ICF1 flag, located in TIFR, is set. * Bit 4 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the OCF1A flag, located in TIFR, is set. * Bit 3 - OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the OCF1B flag, located in TIFR, is set.
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* Bit 2 - TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the TOV1 flag, located in TIFR, is set. ETIMSK - Extended Timer/Counter Interrupt Mask Register(1)
Bit (0x7D) Read/Write Initial Value
7
-
6
-
5
TICIE3
4
OCIE3A
3
OCIE3B
2
TOIE3
1
OCIE3C
0
OCIE1C ETIMSK
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Note:
1. This register is not available in ATmega103 compatibility mode.
* Bit 7:6 - Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be set to zero when ETIMSK is written. * Bit 5 - TICIE3: Timer/Counter3, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the ICF3 flag, located in ETIFR, is set. * Bit 4 - OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the OCF3A flag, located in ETIFR, is set. * Bit 3 - OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the OCF3B flag, located in ETIFR, is set. * Bit 2 - TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the TOV3 flag, located in ETIFR, is set. * Bit 1 - OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the OCF3C flag, located in ETIFR, is set.
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* Bit 0 - OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 61) is executed when the OCF1C flag, located in ETIFR, is set. TIFR - Timer/Counter Interrupt Flag Register(1)
Bit 0x36 (0x56) Read/Write Initial Value
7 OCF2 R/W 0
6 TOV2 R/W 0
5 ICF1 R/W 0
4 OCF1A R/W 0
3 OCF1B R/W 0
2 TOV1 R/W 0
1 OCF0 R/W 0
0 TOV0 R/W 0 TIFR
Note:
1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
* Bit 5 - ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. * Bit 4 - OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. * Bit 3 - OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. * Bit 2 - TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOV1 flag is set when the timer overflows. Refer to Table 61 on page 136 for the TOV1 flag behavior when using another WGMn3:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ETIFR - Extended Timer/Counter Interrupt Flag Register
Bit (0x7C) Read/Write Initial Value
7 - R/W 0
6 - R/W 0
5 ICF3 R/W 0
4 OCF3A R/W 0
3 OCF3B R/W 0
2 TOV3 R/W 0
1 OCF3C R/W 0
0 OCF1C R/W 0 ETIFR
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* Bit 7:6 - Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be set to zero when ETIFR is written. * Bit 5 - ICF3: Timer/Counter3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set when the counter reaches the TOP value. ICF3 is automatically cleared when the Input Capture 3 Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing a logic one to its bit location. * Bit 4 - OCF3A: Timer/Counter3, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register A (OCR3A). Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A flag. OCF3A is automatically cleared when the Output Compare Match 3 A Interrupt Vector is executed. Alternatively, OCF3A can be cleared by writing a logic one to its bit location. * Bit 3 - OCF3B: Timer/Counter3, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B flag. OCF3B is automatically cleared when the Output Compare Match 3 B Interrupt Vector is executed. Alternatively, OCF3B can be cleared by writing a logic one to its bit location. * Bit 2 - TOV3: Timer/Counter3, Overflow Flag The setting of this flag is dependent of the WGM3:0 bits setting. In Normal and CTC modes, the TOV3 flag is set when the timer overflows. Refer to Table 52 on page 104 for the TOV3 flag behavior when using another WGM3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, OCF3B can be cleared by writing a logic one to its bit location. * Bit 1 - OCF3C: Timer/Counter3, Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register C (OCR3C). Note that a Forced Output Compare (FOC3C) strobe will not set the OCF3C flag. OCF3C is automatically cleared when the Output Compare Match 3 C Interrupt Vector is executed. Alternatively, OCF3C can be cleared by writing a logic one to its bit location. * Bit 0 - OCF1C: Timer/Counter1, Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register C (OCR1C). Note that a Forced Output Compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C Interrupt Vector is executed. Alternatively, OCF1C can be cleared by writing a logic one to its bit location.
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Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers
Internal Clock Source
Timer/Counter3, Timer/Counter2 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all of the mentioned Timer/Counters.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. The prescaler is free running, for example, it operates independently of the Clock Select logic of the Timer/Counter, and it is shared by Timer/Counter1, Timer/Counter2, and Timer/Counter3. Since the prescaler is not affected by the Timer/Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also use prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it is connected to.
Prescaler Reset
External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkT1/clkT2/clkT3). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 59 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT2/clkT3 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 59. Tn Pin Sampling
Tn
DQ LE
DQ
D
Q
Tn_sync (To Clock Select Logic)
clk I/O
Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3(1)
CK
Clear
CK/8
10-BIT T/C PRESCALER
CK/256 CK/1024 CK/64
PSR321
T3
0
T2
0
T1
0
CS30 CS31 CS32
CS20 CS21 CS22
CS10 CS11 CS12
TIMER/COUNTER3 CLOCK SOURCE clkT3
TIMER/COUNTER2 CLOCK SOURCE clkT2
TIMER/COUNTER1 CLOCK SOURCE clkT1
Note:
1. The synchronization logic on the input pins (T3/T2/T1) is shown in Figure 59.
SFIOR - Special Function IO Register
Bit 0x20 (0x40) Read/Write Initial Value
7 TSM R/W 0
6 - R 0
5 - R 0
4 - R 0
3 ACME R/W 0
2 PUD R/W 0
1 PSR0 R/W 0
0 PSR321 R/W 0 SFIOR
* Bit 7 - TSM: Timer/Counter Synchronization Mode Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit written zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. * Bit 0 - PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 When this bit is one, the Timer/Counter3, Timer/Counter2, and Timer/Counter1 prescaler will be reset. The bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect all three timers.
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8-bit Timer/Counter2 with PWM
Timer/Counter2 is a general purpose, single-channel, 8-bit Timer/Counter module. The main features are: * Single Channel Counter * Clear Timer on Compare Match (Auto Reload) * Glitch-free, Phase Correct Pulse width Modulator (PWM) * Frequency Generator * External Event Counter * 10-bit Clock Prescaler * Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 61. For the actual placement of I/O pins, refer to "Pin Configuration" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "8-bit Timer/Counter Register Description" on page 157. Figure 61. 8-bit Timer/Counter Block Diagram
Overview
TCCRn
count clear direction Control Logic Clock Select Edge Detector BOTTOM TOP
TOVn (Int.Req.) clk Tn
Tn
DATA BUS
( From Prescaler ) Timer/Counter TCNTn
=0
= 0xFF
OCn (Int.Req.)
=
Waveform Generation
OCn
OCRn
Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T2 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2).
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The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC2). For details, see "Output Compare Unit" on page 148. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in Table 63 are also used extensively throughout this section. Table 63. Definitions BOTTOM MAX TOP The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation.
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS22:0) bits located in the Timer/Counter Control Register (TCCR2). For details on clock sources and prescaler, see "Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers" on page 144.
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Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 62 shows a block diagram of the counter and its surroundings. Figure 62. Counter Unit Block Diagram
TOVn (Int.Req.)
DATA BUS
Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn
Signal description (internal signals): count direction clear clkTn top bottom Increment or decrement TCNT2 by 1. Select between increment and decrement. Clear TCNT2 (set all bits to zero). Timer/counter clock, referred to as clkT0 in the following. Signalize that TCNT2 has reached maximum value. Signalize that TCNT2 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC2. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 151. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation
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(see "Modes of Operation" on page 151). Figure 63 shows a block diagram of the Output Compare unit. Figure 63. Output Compare Unit, Block Diagram
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top bottom FOCn
Waveform Generator
OCn
WGMn1:0
COMn1:0
The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). All CPU write operations to the TCNT2 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled.
Compare Match Blocking by TCNT2 Write
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Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bits in Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately.
Compare Match Output Unit
The Compare Output mode (COM21:0) bits have two functions. The Waveform Generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 64 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. If a System Reset occur, the OC2 Register is reset to "0". Figure 64. Compare Match Output Unit, Schematic
COMn1 COMn0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCn D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC2) from the Waveform Generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port 150
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pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See "8-bit Timer/Counter Register Description" on page 157. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the Waveform Generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 65 on page 158. For fast PWM mode, refer to Table 66 on page 158, and for phase correct PWM refer to Table 67 on page 159. A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits.
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (see "Compare Match Output Unit" on page 150). For detailed timing information refer to Figure 68, Figure 69, Figure 70, and Figure 71 in "Timer/Counter Timing Diagrams" on page 155.
Normal Mode
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 65. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared.
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Figure 65. CTC Mode, Timing Diagram
OCn Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMn1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCn = ---------------------------------------------2 N ( 1 + OCRn ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dualslope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 66. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes
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non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent Compare Matches between OCR2 and TCNT2. Figure 66. Fast PWM Mode, Timing Diagram
OCRn Interrupt Flag Set
OCRn Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to three (see Table 66 on page 158). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnPWM = ----------------N 256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
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Phase Correct PWM Mode
The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 67. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent Compare Matches between OCR2 and TCNT2. Figure 67. Phase Correct PWM Mode, Timing Diagram
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to three (see Table 67 on page 159). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match
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between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 67 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without a Compare Match. * OCR2 changes its value from MAX, like in Figure 67. When the OCR2 value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. The timer starts counting from a higher value than the one in OCR2, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up.
*
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT2) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 68 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 68. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 69 shows the same timing data, but with the prescaler enabled.
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Figure 69. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 70 shows the setting of OCF2 in all modes except CTC mode. Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
Figure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
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Figure 71. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
8-bit Timer/Counter Register Description
TCCR2 - Timer/Counter Control Register
Bit 0x25 (0x45) Read/Write Initial Value 7 FOC2 W 0 6 WGM20 R/W 0 5 COM21 R/W 0 4 COM20 R/W 0 3 WGM21 R/W 0 2 CS22 R/W 0 1 CS21 R/W 0 0 CS20 R/W 0 TCCR2
* Bit 7 - FOC2: Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. * Bit 6, 3 - WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 64 and "Modes of Operation" on page 151.
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Table 64. Waveform Generation Mode Bit Description(1)
Mode 0 1 2 3 Note: WGM21 (CTC2) 0 0 1 1 WGM20 (PWM2) 0 1 0 1 Timer/Counter Mode of Operation Normal PWM, Phase Correct CTC Fast PWM TOP 0xFF 0xFF OCR2 0xFF Update of OCR2 Immediate TOP Immediate BOTTOM TOV2 Flag Set on MAX BOTTOM MAX MAX
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.
* Bit 5:4 - COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 65 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a Normal or CTC mode (non-PWM). Table 65. Compare Output Mode, non-PWM Mode
COM21 0 0 1 1 COM20 0 1 0 1 Description Normal port operation, OC2 disconnected. Toggle OC2 on Compare Match. Clear OC2 on Compare Match. Set OC2 on Compare Match.
Table 66 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 66. Compare Output Mode, Fast PWM Mode(1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 Description Normal port operation, OC2 disconnected. Reserved Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode). Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode).
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM Mode" on page 152 for more details.
Table 67 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode.
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Table 67. Compare Output Mode, Phase Correct PWM Mode(1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 Description Normal port operation, OC2 disconnected. Reserved Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting. Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting.
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 154 for more details.
* Bit 2:0 - CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 68. Clock Select Bit Description
CS22 0 0 0 0 1 1 1 1 CS21 0 0 1 1 0 0 1 1 CS20 0 1 0 1 0 1 0 1 Description No clock source (Timer/counter stopped). clkI/O/(No prescaling) clkI/O/8 (From prescaler) clkI/O/64 (From prescaler) clkI/O/256 (From prescaler) clkI/O/1024 (From prescaler) External clock source on T2 pin. Clock on falling edge. External clock source on T2 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. TCNT2 - Timer/Counter Register
Bit 0x24 (0x44) Read/Write Initial Value
7
6
5
4
3
2
1
0 TCNT2
TCNT2[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register.
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OCR2 - Output Compare Register
Bit 0x23 (0x43) Read/Write Initial Value
7
6
5
4
3
2
1
0 OCR2
OCR2[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin. TIMSK - Timer/Counter Interrupt Mask Register
Bit 0x37 (0x57) Read/Write Initial Value
7 OCIE2 R/W 0
6 TOIE2 R/W 0
5 TICIE1 R/W 0
4 OCIE1A R/W 0
3 OCIE1B R/W 0
2 TOIE1 R/W 0
1 OCIE0 R/W 0
0 TOIE0 R/W 0 TIMSK
* Bit 7 - OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs, for example, when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, for example, when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. TIFR - Timer/Counter Interrupt Flag Register
Bit 0x36 (0x56) Read/Write Initial Value
7 OCF2 R/W 0
6 TOV2 R/W 0
5 ICF1 R/W 0
4 OCF1A R/W 0
3 OCF1B R/W 0
2 TOV1 R/W 0
1 OCF0 R/W 0
0 TOV0 R/W 0 TIFR
* Bit 7 - OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. * Bit 6 - TOV2: Timer/Counter2 Overflow Flag The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
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Output Compare Modulator (OCM1C2)
Overview
The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details about these Timer/Counters see "16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)" on page 112 and "8-bit Timer/Counter2 with PWM" on page 146. Note that this feature is not available in ATmega103 compatibility mode. Figure 72. Output Compare Modulator, Block Diagram
Timer/Counter1
OC1C
Pin OC1C/ OC2/PB7
Timer/Counter2
OC2
When the modulator is enabled, the two Output Compare channels are modulated together as shown in the block diagram (Figure 72).
Description
The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The outputs of the Output Compare units (OC1C and OC2) overrides the normal PORTB7 Register when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both OC1C and OC2 are enabled at the same time, the modulator is automatically enabled. The functional equivalent schematic of the modulator is shown on Figure 73. The schematic includes part of the Timer/Counter units and the Port B pin 7 output driver circuit. Figure 73. Output Compare Modulator, Schematic
COM21 COM20 COM1C1 COM1C0
Modulator Vcc
0 1
( From Waveform Generator )
D
Q
OC1C
( From Waveform Generator )
1 Pin 0 OC1C / OC2 / PB7
D
Q
OC2 D Q D Q
PORTB7 DATA BUS
DDRB7
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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. Timing Example Figure 74 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 74. Output Compare Modulator, Timing Diagram
clk I/O OC1C
(FPWM Mode)
OC2
(CTC Mode)
PB7
(PORTB7 = 0)
PB7
(PORTB7 = 1) 1 2 3
(Period)
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated by the Output Compare unit C of the Timer/Counter1. The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC2). In this example the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure 74 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the period three high time, but the result on the PB7 output is equal in both periods.
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SPI - Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega64 and peripheral devices or between several AVR devices. The ATmega64 SPI includes the following features: * Full-duplex, Three-wire Synchronous Data Transfer * Master or Slave Operation * LSB First or MSB First Data Transfer * Seven Programmable Bit Rates * End of Transmission Interrupt Flag * Write Collision Flag Protection * Wake-up from Idle Mode * Double Speed (CK/2) Master SPI Mode Figure 75. SPI Block Diagram(1)
DIVIDER /2/4/8/16/32/64/128
SPI2X
Note:
1. Refer to Figure 1 on page 2, and Table 30 on page 74 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 76. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is
SPI2X
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done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the buffer register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the buffer register for later use. Figure 76. SPI Master-Slave Interconnection
MSB MASTER LSB MISO MOSI MISO MOSI SHIFT ENABLE SPI CLOCK GENERATOR SCK SS VCC SCK SS MSB SLAVE LSB 8 BIT SHIFT REGISTER 8 BIT SHIFT REGISTER
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: Low periods: Longer than 2 CPU clock cycles. High periods: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 69. For more details on automatic port overrides, refer to "Alternate Port Functions" on page 71. Table 69. SPI Pin Overrides(1)
Pin MOSI MISO SCK SS Direction, Master SPI User Defined Input User Defined User Defined Direction, Slave SPI Input User Defined Input Input
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Note: 1. See "Alternate Functions of Port B" on page 74 for a detailed description of how to define the direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Assembly Code Example(1)
SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1<; Enable SPI, Master, set clock rate fck/16
C Code Example(1)
void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<Note:
1. See "About Code Examples" on page 9.
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example(1)
SPI_SlaveInit: ; Set MISO output, all others input ldi out ldi out ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in ret r16,SPDR r17,(1<; Enable SPI
C Code Example(1)
void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDR_SPI = (1<Note:
1. See "About Code Examples" on page 9.
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SS Pin Functionality
Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the Master clock generator. When the SS pin is driven high, the SPI Slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI Slave. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another Master selecting the SPI as a Slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. SPCR - SPI Control Register
Bit 0x0D (0x2D) Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. * Bit 6 - SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. * Bit 5 - DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first.
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* Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. * Bit 3 - CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL functionality is summarized below: Table 70. CPOL Functionality
CPOL 0 1 Leading Edge Rising Falling Trailing Edge Falling Rising
* Bit 2 - CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 77 and Figure 78 for an example. The CPHA functionality is summarized below: Table 71. CPHA Functionality
CPHA 0 1 Leading Edge Sample Setup Trailing Edge Setup Sample
* Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in Table 72. Table 72. Relationship Between SCK and the Oscillator Frequency
SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK Frequency
fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64
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SPSR - SPI Status Register
Bit 0x0E (0x2E) Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). * Bit 6 - WCOL: Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. * Bit 5..1 - Res: Reserved Bits These bits are reserved bits in the ATmega64 and will always read as zero. * Bit 0 - SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 72). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower. The SPI interface on the ATmega64 is also used for program memory and EEPROM downloading or uploading. See page 307 for SPI Serial Programming and verification. SPDR - SPI Data Register
Bit 0x0F (0x2F) Read/Write Initial Value 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X Undefined SPDR
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
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Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 77 and Figure 78. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 70 and Table 71, as done below: Table 73. CPOL and CPHA Functionality
Leading Edge CPOL = 0, CPHA = 0 CPOL = 0, CPHA = 1 CPOL = 1, CPHA = 0 CPOL = 1, CPHA = 1 Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) SPI Mode 0 1 2 3
Figure 77. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 78. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
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USART
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: * Full Duplex Operation (Independent Serial Receive and Transmit Registers) * Asynchronous or Synchronous Operation * Master or Slave Clocked Synchronous Operation * High Resolution Baud Rate Generator * Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits * Odd or Even Parity Generation and Parity Check Supported by Hardware * Data OverRun Detection * Framing Error Detection * Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter * Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete * Multi-processor Communication Mode * Double Speed Asynchronous Communication Mode The ATmega64 has two USART's, USART0 and USART1. The functionality for both USART's is described below. USART0 and USART1 have different I/O Registers as shown in "Register Summary" on page 372. Note that in ATmega103 compatibility mode, USART1 is not available, neither is the UBRR0H or UCRS0C registers. This means that in ATmega103 compatibility mode, the ATmega64 supports asynchronous operation of USART0 only. A simplified block diagram of the USART Transmitter is shown in Figure 79. CPU accessible I/O Registers and I/O pins are shown in bold. Figure 79. USART Block Diagram(1)
Clock Generator
UBRR[H:L] OSC
Dual USART
Overview
BAUD RATE GENERATOR
SYNC LOGIC
PIN CONTROL
XCK
Transmitter
DATA BUS
UDR (Transmit) PARITY GENERATOR TRANSMIT SHIFT REGISTER
TX CONTROL
PIN CONTROL
TxD
Receiver
CLOCK RECOVERY RX CONTROL
RECEIVE SHIFT REGISTER
DATA RECOVERY
PIN CONTROL
RxD
UDR (Receive)
PARITY CHECKER
UCSRA
UCSRB
UCSRC
Note:
1. Refer to Figure 1 on page 2, Table 36 on page 78, and Table 39 on page 81 for USART pin placement.
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The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control Logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control Logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. AVR USART vs. AVR UART - Compatibility The USART is fully compatible with the AVR UART regarding: * * * * * Bit locations inside all USART Registers Baud Rate Generation. Transmitter Operation. Transmit Buffer Functionality. Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some special cases: * A second buffer register has been added. The two buffer registers operate as a circular FIFO buffer. Therefore the UDRn must only be read once for each incoming data! More important is the fact that the error flags (FEn and DORn) and the ninth data bit (RXB8n) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDRn Register is read. Otherwise the error status will be lost since the buffer state is lost. The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see Figure 79) if the buffer registers are full, until a new start bit is detected. The USART is therefore more resistant to Data Over Run (DORn) error conditions.
*
The following control bits have changed name, but have same functionality and register location: * * CHR9 is changed to UCSZn2. OR is changed to DORn.
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART Control and Status Register n C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnB Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 80 shows a block diagram of the Clock Generation logic.
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Figure 80. Clock Generation Logic, Block Diagram
UBRR fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 U2X
0 1
OSC DDR_XCK Sync Register Edge Detector
0 1
txclk
xcki XCK Pin xcko
0 1
UMSEL
DDR_XCK
UCPOL
1 0
rxclk
Signal description: txclk rxclk xcki xcko fosc Internal Clock Generation - The Baud Rate Generator Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock).
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 80. The USART Baud Rate Register n (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fOSC), is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fOSC/(UBRRn+1)). The transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator output is used directly by the receiver's clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCK bits. Table 74 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source.
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Table 74. Equations for Calculating Baud Rate Register Setting
Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: Equation for Calculating Baud Rate(1) Equation for Calculating UBRR Value
f OSC BAUD = ----------------------------------------16 ( UBRR + 1n ) f OSC BAUD = -------------------------------------8 ( UBRRn + 1 ) f OSC BAUD = -------------------------------------2 ( UBRR + 1n )
f OSC UBRRn = ----------------------- - 1 16BAUD f OSC UBRRn = ------------------- - 1 8BAUD f OSC UBRRn = ------------------- - 1 2BAUD
1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency
UBRR Contents of the UBRRnH and UBRRnL Registers, (0 - 4095) Some examples of UBRRn values for some system clock frequencies are found in Table 82 on page 194 to Table 85 on page 197. Double Speed Operation (U2Xn) The transfer rate can be doubled by setting the U2Xn bit in UCSRnB. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides. External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 80 for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: f OSC f XCK < ---------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed.
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Figure 81. Synchronous Mode XCK Timing
UCPOLn = 1 XCK
RxD / TxD Sample UCPOLn = 0 XCK
RxD / TxD Sample
The UCPOLn bit UCRSnC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 81 shows, when UCPOLn is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: * * * * 1 start bit 5, 6, 7, 8, or 9 data bits no, even or odd parity bit 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 82 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 82. Frame Formats
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St (n) P Sp IDLE
Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. No transfers on the communication line (RxD or TxD). An IDLE line must be high.
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
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Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character Size (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select n (USBSn) bit. The receiver ignores the second stop bit. An FEn (Frame Error n) will therefore only be detected in the cases where the first stop bit is zero. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows:: P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn Parity bit using even parity Parity bit using odd parity Data bit n of the character
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
USART Initialization
The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn flag can be used to check that the Transmitter has completed all transfers, and the RXCn flag can be used to check that there are no unread data in the receive buffer. Note that the TXCn flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers.
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Assembly Code Example(1)
USART_Init: ; Set baud rate out out ldi out ldi out ret UBRRnH, r17 UBRRnL, r16 r16, (1<; Enable receiver and transmitter
; Set frame format: 8data, 2stop bit
C Code Example(1)
void USART_Init( unsigned int baud ) { /* Set baud rate */ UBRRnH = (unsigned char)(baud>>8); UBRRnL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRnB = (1<Note:
1. See "About Code Examples" on page 9.
More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules.
Data Transmission - The USART Transmitter
The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the transmitter's serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock. A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the baud register, U2Xn bit or by XCK depending on mode of operation. The following code examples show a simple USART transmit function based on polling of the Data Register Empty (UDREn) flag. When using frames with less than eight bits, the most significant bits written to the UDRn are ignored. The USART has to be initial-
Sending Frames with 5 to 8 Data Bits
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ized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in register R16 Assembly Code Example(1)
USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out ret UDRn,r16
C Code Example(1)
void USART_Transmit( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<Note:
1. See "About Code Examples" on page 9. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
The function simply waits for the transmit buffer to be empty by checking the UDREn flag, before loading it with new data to be transmitted. If the Data Register Empty Interrupt is utilized, the interrupt routine writes the data into the buffer.
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Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers r17:r16. Assembly Code Example(1)
USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy ninth bit from r17 to TXB8 cbi sbi out ret UCSRnB,TXB8n UCSRnB,TXB8n UDRn,r16 sbrc r17,0 ; Put LSB data (r16) into buffer, sends the data
C Code Example(1)
void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<Note:
1. These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRnB is static. For example, only the TXB8n bit of the UCSRnB Register is used after initialization. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
The ninth bit can be used for indicating an address frame when using Multi-processor Communication mode or for other protocol handling as for example synchronization.
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Transmitter Flags and Interrupts
The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete n (TXCn) flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag is useful in half-duplex communication interfaces (like the RS-485 standard), where a transmitting application must enter Receive mode and free the communication bus immediately after completing the transmission. When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART Transmit Complete Interrupt will be executed when the TXCn flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXCn flag, this is done automatically when the interrupt is executed.
Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMn1 = 1), the Transmitter Control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD pin.
Disabling the Transmitter
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Data Reception - The USART Receiver
The USART Receiver is enabled by writing the Receive Enable n (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver's serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock. The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete n (RXCn) flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1)
USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in ret r16, UDRn
Receiving Frames with 5 to 8 Data Bits
C Code Example(1)
unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<Note:
1. See "About Code Examples" on page 9.
The function simply waits for data to be present in the receive buffer by checking the RXCn flag, before reading the buffer and returning the value.
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Receiving Frames with 9 Data Bits
If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDR. This rule applies to the FEn, DORn, and UPE status flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn, and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example(1)
USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and ninth bit, then data from buffer in in in r18, UCSRnA r17, UCSRnB r16, UDRn
; If error, return -1 andi r18,(1<USART_ReceiveNoError: ; Filter the ninth bit, then return lsr ret r17 andi r17, 0x01
C Code Example(1)
unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* Wait for data to be received */ while ( !(UCSRnA & (1<> 1) & 0x01; return ((resh << 8) | resl); }
Note:
1. See "About Code Examples" on page 9.
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The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete n (RXCn) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e. does not contain any unread data). If the receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable n (RXCIEn) in UCSRnB is set, the USART Receive Complete Interrupt will be executed as long as the RXCn flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn flag, otherwise a new interrupt will occur once the interrupt routine terminates. Receiver Error Flags The USART Receiver has three error flags: Frame Error n (FEn), Data OverRun n (DORn) and USART Parity Error n (UPEn). All can be accessed by reading UCSRnA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error n (FEn) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn flag is zero when the stop bit was correctly read (as one), and the FEn flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun n (DORn) flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The USART Parity Error n (UPEn) flag indicates that the next frame in the receive buffer had a Parity Error when received. If parity check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see "Parity Bit Calculation" on page 176 and "Parity Checker" on page 183. Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity
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Error n (UPEn) flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e. the RXENn is set to zero) the receiver will no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn flag is cleared. The following code examples show how to flush the receive buffer. Assembly Code Example(1)
USART_Flush: sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush
Flushing the Receive Buffer
C Code Example(1)
void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA & (1<Note:
1. See "About Code Examples" on page 9.
Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. The Clock Recovery logic synchronizes internal clock to the incoming serial frames. Figure 83 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity).
Asynchronous Clock Recovery
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Figure 83. Start Bit Sampling
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
When the Clock Recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The Clock Recovery logic then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit. Asynchronous Data Recovery When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode. Figure 84 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is equal to the state of the recovery unit. Figure 84. Sampling of Data and Parity Bit
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure by having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the receiver only uses the first stop bit of a frame. Figure 85 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame.
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Figure 85. Stop Bit Sampling and Next Start Bit Sampling
RxD STOP 1
(A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error n (FEn) flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 85. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the operational range of the Receiver. Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see Table 75) base frequency, the Receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. ( D + 1 )S R slow = -----------------------------------------S - 1 + D S + SF D S SF SM ( D + 2 )S R fast = ----------------------------------( D + 1 )S + S M
Sum of character size and parity size (D = 5 to 10 bit) Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode. First sample number used for majority voting. SF = 8 for Normal Speed and SF = 4 for Double Speed mode. Middle sample number used for majority voting. SM = 9 for Normal Speed and SM = 5 for Double Speed mode.
Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. Table 75 and Table 76 list the maximum Receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations.
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Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0)
D # (Data+Parity Bit) 5 6 7 8 9 10 Rslow (%) 93.20 94.12 94.81 95.36 95.81 96.17 Rfast (%) 106.67 105.79 105.11 104.58 104.14 103.78 Max Total Error (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 Recommended Max Receiver Error (%) 3.0 2.5 2.0 2.0 1.5 1.5
Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1)
D # (Data+Parity Bit) 5 6 7 8 9 10 Rslow (%) 94.12 94.92 95.52 96.00 96.39 96.70 Rfast (%) 105.66 104.92 104.35 103.90 103.53 103.23 Max Total Error (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 Recommended Max Receiver Error (%) 2.5 2.0 1.5 1.5 1.5 1.0
The recommendations of the maximum receiver baud rate error was made under the assumption that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. The receiver's system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible.
Multi-processor Communication Mode
Setting the Multi-processor Communication mode n (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn setting, but has to be used differently when it is a part of a system utilizing the Multi-processor Communication mode. If the Receiver is set up to receive frames that contain five to eight data bits, then the first stop bit indicates if the frame contains data or address information. If the receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame.
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The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular Slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame (TXBn = 0) is being transmitted. The Slave MCUs must in this case be set to use a 9-bit character frame format. The following procedure should be used to exchange data in Multi-processor Communication mode: 1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is set). 2. The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXCn flag in UCSRnA will be set as normal. 3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from Master. The process then repeats from 2. Using any of the 5- to 8-bit character frame formats is possible, but impractical since the Receiver must change between using n and n+1 character frame formats. This makes full duplex operation difficult since the Transmitter and Receiver uses the same character size setting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type. Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCMn bit shares the same I/O location as the TXCn flag and this might accidentally be cleared when using SBI or CBI instructions.
USART Register Description
UDRn - USART I/O Data Register
Bit 7 6 5 4 RXB[7:0] TXB[7:0] Read/Write Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 UDnR (Read) UDnR (Write)
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXBn) will be the destination for data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the Receive Data Buffer Register (RXBn). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. 188
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The transmit buffer can only be written when the UDREn flag in the UCSRnA Register is set. Data written to UDRn when the UDREn flag is not set, will be ignored by the USART transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. UCSRnA - USART Control and Status Register A
Bit
7 RXCn
6 TXCn R/W 0
5 UDREn R 1
4 FEn R 0
3 DORn R 0
2 UPEn R 0
1 U2Xn R/W 0
0 MPCMn R/W 0 UCSRnA
Read/Write Initial Value
R 0
* Bit 7 - RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit). * Bit 6 - TXCn: USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR). The TXC flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag can generate a Transmit Complete interrupt (see description of the TXCIE bit). * Bit 5 - UDREn: USART Data Register Empty The UDREn flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. * Bit 4 - FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. For example, when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA. * Bit 3 - DORn: Data OverRun This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
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* Bit 2 - UPEn: USART Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. * Bit 1 - U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. * Bit 0 - MPCMn: Multi-processor Communication Mode This bit enables the Multi-processor Communication Mode. When the MPCMn bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed information see "Multi-processor Communication Mode" on page 187. UCSRnB - USART Control and Status Register B
Bit
7 RXCIEn
6 TXCIEn R/W 0
5 UDRIEn R/W 0
4 RXENn R/W 0
3 TXENn R/W 0
2 UCSZn2 R/W 0
1 RXB8n R 0
0 TXB8n R/W 0 UCSRnB
Read/Write Initial Value
R/W 0
* Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn flag. A USART Receive Complete interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set. * Bit 6 - TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. * Bit 5 - UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. * Bit 4 - RXENn: Receiver Enable Writing this bit to one enables the USART receiver. The Receiver will override normal port operation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn flags. * Bit 3 - TXENn: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register
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do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD port. * Bit 2 - UCSZn2: Character Size The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRC sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. * Bit 1 - RXB8n: Receive Data Bit 8 RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDRn. * Bit 0 - TXB8n: Transmit Data Bit 8 TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. UCSRnC - USART Control and Status Register C(1)
Bit
7 -
6 UMSELn R/W 0
5 UPMn1 R/W 0
4 UPMn0 R/W 0
3 USBSn R/W 0
2 UCSZn1 R/W 1
1 UCSZn0 R/W 1
0 UCPOLn R/W 0 UCSRnC
Read/Write Initial Value
R/W 0
Note:
1. This register is not available in ATmega103 compatibility mode.
* Bit 7 - Reserved Bit This bit is reserved for future use. For compatibility with future devices, this bit must be written to zero when UCSRC is written. * Bit 6 - UMSELn: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 77. UMSEL Bit Settings
UMSELn 0 1 Mode Asynchronous Operation Synchronous Operation
* Bit 5:4 - UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn flag in UCSRnB will be set. Table 78. UPM Bits Settings
UPMn1 0 0 1 1 UPMn0 0 1 0 1 Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity
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* Bit 3 - USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 79. USBS Bit Settings
USBSn 0 1 Stop Bit(s) 1-bit 2-bit
* Bit 2:1 - UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Table 80. UCSZ Bits Settings
UCSZn2 0 0 0 0 1 1 1 1 UCSZn1 0 0 1 1 0 0 1 1 UCSZn0 0 1 0 1 0 1 0 1 Character Size 5-bit 6-bit 7-bit 8-bit Reserved Reserved Reserved 9-bit
* Bit 0 - UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 81. UCPOL Bit Settings
UCPOLn 0 1 Transmitted Data Changed (Output of TxD Pin) Rising XCK Edge Falling XCK Edge Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge
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UBRRnL and UBRRnH - USART Baud Rate Registers(1)
Bit 15 - 14 - 13 - 12 - UBRRn[7:0] 7 Read/Write R R/W Initial Value 0 0 6 R R/W 0 0 5 R R/W 0 0 4 R R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 11 10 9 8 UBRRnH UBRRnL
UBRRn[11:8]
Note:
1. UBRRH is not available in mega103 compatibility mode
* Bit 15:12 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. * Bit 11:0 - UBRRn11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four most significant bits, and the UBRRnL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.
Examples of Baud Rate Setting
For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRRn settings in Table 82 to Table 85. UBRRn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see "Asynchronous Operational Range" on page 186). The error values are calculated using the following equation:
BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate
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Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies
fosc = 1.0000 MHz Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k Max 1.
(1)
fosc = 1.8432 MHz U2X = 0 UBRRn 47 23 11 7 5 3 2 1 1 0 - - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - - U2X = 1 UBRRn 95 47 23 15 11 7 5 3 2 1 0 - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -
fosc = 2.0000 MHz U2X = 0 UBRRn 51 25 12 8 6 3 2 1 1 0 - - 125 kbps Error 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - U2X = 1 UBRRn 103 51 25 16 12 8 6 3 2 1 - 0 Error 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0%
U2X = 0 UBRRn 25 12 6 3 2 1 1 0 - - - - 62.5 kbps UBRR = 0, Error = 0.0% Error 0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - -
U2X = 1 UBRRn 51 25 12 8 6 3 2 1 1 0 - - 125 kbps Errorn 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - -
115.2 kbps
230.4 kbps
250 kbps
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Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
fosc = 3.6864 MHz Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M Max 1.
(1)
fosc = 4.0000 MHz U2X = 0 UBRRn 103 51 25 16 12 8 6 3 2 1 0 0 - - 250 kbps Error 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - - U2X = 1 UBRRn 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.5 Mbps Error 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
fosc = 7.3728 MHz U2X = 0 UBRRn 191 95 47 31 23 15 11 7 5 3 1 1 0 - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - U2X = 1 UBRRn 383 191 95 63 47 31 23 15 11 7 3 3 1 0 Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
U2X = 0 UBRRn 95 47 23 15 11 7 5 3 2 1 0 0 - - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
U2X = 1 UBRRn 191 95 47 31 23 15 11 7 5 3 1 1 0 - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -
230.4 kbps UBRR = 0, Error = 0.0%
460.8 kbps
460.8 kbps
921.6 kbps
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Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
fosc = 8.0000 MHz Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M Max 1.
(1)
fosc = 11.0592 MHz U2X = 0 UBRRn 287 143 71 47 35 23 17 11 8 5 2 2 - - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRRn 575 287 143 95 71 47 35 23 17 11 5 5 2 - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -
fosc = 14.7456 MHz U2X = 0 UBRRn 383 191 95 63 47 31 23 15 11 7 3 3 1 0 Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 1 UBRRn 767 383 191 127 95 63 47 31 23 15 7 6 3 1 Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8%
U2X = 0 UBRRn 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.5 Mbps UBRR = 0, Error = 0.0% Error 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
U2X = 1 UBRRn 416 207 103 68 51 34 25 16 12 8 3 3 1 0 Error -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1 Mbps
691.2 kbps
1.3824 Mbps
921.6 kbps
1.8432 Mbps
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Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
fosc = 16.0000 MHz Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M Max 1.
(1)
fosc = 18.4320 MHz U2X = 0 UBRRn 479 239 119 79 59 39 29 19 14 9 4 4 - - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRRn 959 479 239 159 119 79 59 39 29 19 9 8 4 - Error 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 2.4% -7.8% -
fosc = 20.0000 MHz U2X = 0 UBRRn 520 259 129 86 64 42 32 21 15 10 4 4 - - Error 0.0% 0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% 1.7% -1.4% 8.5% 0.0% - - U2X = 1 UBRRn 1041 520 259 173 129 86 64 42 32 21 10 9 4 - 2.5 Mbps Error 0.0% 0.0% 0.2% -0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% -1.4% 0.0% 0.0% -
U2X = 0 UBRRn 416 207 103 68 51 34 25 16 12 8 3 3 1 0 Error -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1 Mbps UBRR = 0, Error = 0.0%
U2X = 1 UBRRn 832 416 207 138 103 68 51 34 25 16 8 7 3 1 Error 0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0% 2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
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TWI - Two-wire Serial Interface
Features
* * * * * * * * * *
Simple yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed Both Master and Slave Operation Supported Device can Operate as Transmitter or Receiver 7-bit Address Space allows up to 128 Different Slave Addresses Multi-master Arbitration Support Up to 400 kHz Data Transfer Speed Slew-rate Limited Output Drivers Noise Suppression Circuitry Rejects Spikes on Bus Lines Fully Programmable Slave Address with General Call Support Address Recognition Causes Wake-up when AVR is in Sleep Mode
Two-wire Serial Interface Bus Definition
The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 86. TWI Bus Interconnection
VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
TWI Terminology
The following definitions are frequently encountered in this section. Table 86. TWI Terminology
Term Master Slave Transmitter Receiver Description The device that initiates and terminates a transmission. The Master also generates the SCL clock. The device addressed by a Master. The device placing data on the bus. The device reading data from the bus.
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Electrical Interconnection As depicted in Figure 86, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in "Two-wire Serial Interface Characteristics" on page 330. Two different sets of specifications are presented there, one relevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz.
Data Transfer and Frame Format
Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 87. Data Validity
SDA
SCL Data Stable Data Stable
Data Change
START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other Master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED START condition, and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. This is identical to the START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this data sheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high.
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Figure 88. START, REPEATED START, and STOP Conditions
SDA
SCL
START
STOP START
REPEATED START
STOP
Address Packet Format
All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Master's request, the SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a Master wishes to transmit the same message to several slaves in the system. When the general call address followed by a write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 89. Address Packet Format
Addr MSB SDA Addr LSB R/W ACK
SCL 1 START 2 7 8 9
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Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 90. Data Packet Format
Data MSB Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 SLA+R/W 2 7 Data Byte 8 9 STOP, REPEATED START, or Next Data Byte Data LSB ACK
Combining Address and Data Packets Into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the Slave, or the Slave needs extra time for processing between the data transmissions. The Slave extending the SCL low period will not affect the SCL high period, which is determined by the Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. Figure 91 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software. Figure 91. Typical Data Transmission
Addr MSB SDA Addr LSB R/W ACK Data MSB Data LSB ACK
SCL 1 START 2 7 SLA+R/W 8 9 1 2 Data Byte 7 8 9 STOP
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Multi-master Bus The TWI protocol allows bus systems with several masters. Special concerns have Systems, Arbitration and been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-masSynchronization
ter systems: * An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves (i.e., the data being transferred on the bus must not be corrupted). Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process.
*
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the master with the shortest high period. The low period of the combined clock is equal to the low period of the master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low Time-out periods when the combined SCL line goes high or low, respectively. Figure 92. SCL Synchronization between Multiple Masters
TA low
TA high
SCL from Master A
SCL from Master B
SCL bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the master had output, it has lost the arbitration. Note that a master can only lose arbitration when it outputs a high SDA value while another master outputs a low value. The losing master should immediately go to Slave mode, checking if it is being addressed by the winning master. The SDA line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one master remains, and this may take many bits. If several masters are trying to address the same slave, arbitration will continue into the data packet.
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Figure 93. Arbitration between Two Masters
START SDA from Master A Master A Loses Arbitration, SDAA SDA
SDA from M
SDA Line
Synchronized SCL Line
Note that arbitration is not allowed between: * * * A REPEATED START condition and a data bit. A STOP condition and a data bit. A REPEATED START and a STOP condition.
It is the user software's responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined.
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Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 94. All registers drawn in a thick line are accessible through the AVR data bus. Figure 94. Overview of the TWI Module
SCL
Slew-rate Control Spike Filter
SDA
Slew-rate Control Spike Filter
Bus Interface Unit
START / STOP Control Spike Suppression
Bit Rate Generator
Prescaler
Arbitration Detection
Address/Data Shift Register (TWDR)
Ack
Bit Rate Register (TWBR)
Address Match Unit
Address Register (TWAR)
Control Unit
Status Register (TWSR) Control Register (TWCR)
Address Comparator
State Machine and Status Control
SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones. This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: CPU Clock frequency SCL frequency = ---------------------------------------------------------TWPS 16 + 2(TWBR) 4 * TWBR = Value of the TWI Bit Rate Register.
Bit Rate Generator Unit
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TWI Unit
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* TWPS = Value of the prescaler bits in the TWI Status Register.
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See Table 133 on page 330 for value of pull-up resistor."
Note:
Bus Interface Unit
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a Master. If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated.
Address Match Unit
The Address Match unit checks if received address bytes match the 7-bit address in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the General Call address. Upon an address match, the Control unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake-up if addressed by a Master. The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI interrupt flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT flag is set in the following situations: * * * * * * * * After the TWI has transmitted a START/REPEATED START condition. After the TWI has transmitted SLA+R/W. After the TWI has transmitted an address byte. After the TWI has lost arbitration. After the TWI has been addressed by own slave address or general call. After the TWI has received a data byte. After a STOP or REPEATED START has been received while still addressed as a Slave. When a bus error has occurred due to an illegal START or STOP condition.
Control Unit
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TWI Register Description
TWBR -TWI Bit Rate Register
Bit (0x70) Read/Write Initial Value 7 TWBR7 R/W 0 6 TWBR6 R/W 0 5 TWBR5 R/W 0 4 TWBR4 R/W 0 3 TWBR3 R/W 0 2 TWBR2 R/W 0 1 TWBR1 R/W 0 0 TWBR0 R/W 0 TWBR
* Bits 7..0 - TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See "Bit Rate Generator Unit" on page 204 for calculating bit rates. TWCR - TWI Control Register
Bit (0x74) Read/Write Initial Value 7 TWINT R/W 0 6 TWEA R/W 0 5 TWSTA R/W 0 4 TWSTO R/W 0 3 TWWC R 0 2 TWEN R/W 0 1 - R 0 0 TWIE R/W 0 TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. * Bit 7 - TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag. * Bit 6 - TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device's own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the Twowire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. * Bit 5 - TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the Two-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim
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the Bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. * Bit 4 - TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. * Bit 3 - TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. * Bit 2 - TWEN: TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. * Bit 1 - Res: Reserved Bit This bit is a reserved bit and will always read as zero. * Bit 0 - TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high. TWSR - TWI Status Register
Bit (0x71) Read/Write Initial Value 7 TWS7 R 1 6 TWS6 R 1 5 TWS5 R 1 4 TWS4 R 1 3 TWS3 R 1 2 - R 0 1 TWPS1 R/W 0 0 TWPS0 R/W 0 TWSR
* Bits 7..3 - TWS: TWI Status These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. * Bit 2 - Res: Reserved Bit This bit is reserved and will always read as zero.
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* Bits 1..0 - TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 87. TWI Bit Rate Prescaler
TWPS1 0 0 1 1 TWPS0 0 1 0 1 Prescaler Value 1 4 16 64
To calculate bit rates, see "Bit Rate Generator Unit" on page 204. The value of TWPS1..0 is used in the equation. TWDR - TWI Data Register
Bit (0x73) Read/Write Initial Value 7 TWD7 R/W 1 6 TWD6 R/W 1 5 TWD5 R/W 1 4 TWD4 R/W 1 3 TWD3 R/W 1 2 TWD2 R/W 1 1 TWD1 R/W 1 0 TWD0 R/W 1 TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake-up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. * Bits 7..0 - TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus. TWAR - TWI (Slave) Address Register
Bit (0x72) Read/Write Initial Value
7 TWA6 R/W 1
6 TWA5 R/W 1
5 TWA4 R/W 1
4 TWA3 R/W 1
3 TWA2 R/W 1
2 TWA1 R/W 1
1 TWA0 R/W 1
0 TWGCE R/W 0 TWAR
The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. * Bits 7..1 - TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit.
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* Bit 0 - TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.
Using the TWI
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in order to detect actions on the TWI bus. When the TWINT flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR registers. Figure 95 is a simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented.
Figure 95. Interfacing the Application to the TWI in a Typical Transmission
Application Action
1. Application writes to TWCR to initiate transmission of START
3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero.
5. Check TWSR to see if SLA+W was sent and ACK received. Application loads data into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one
7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one
TWI bus
START
SLA+W
A
Data
A
STOP
TWI Hardware Action
2. TWINT set. Status code indicates START condition sent
4. TWINT set. Status code indicates SLA+W sent, ACK received
6. TWINT set. Status code indicates data sent, ACK received
Indicates TWINT set
1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. 209
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3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet. 4. When the address packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent. Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: * * When the TWI has finished an operation and expects application response, the TWINT flag is set. The SCL line is pulled low until TWINT is cleared. When the TWINT flag is set, the user must update all TWI registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle. After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be
*
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set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made for example by using include-files.
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Assembly code example(1) 1
ldi out r16, (1<C example(1)
TWCR = (1<Comments Send START condition
2
wait1: in r16,TWCR sbrs r16,TWINT rjmp wait1
Wait for TWINT flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits. If status different from START go to ERROR Load SLA_W into TWDR Register. Clear TWINT bit in TWCR to start transmission of address Wait for TWINT flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received. Check value of TWI Status Register. Mask prescaler bits. If status different from MT_SLA_ACK go to ERROR Load DATA into TWDR Register. Clear TWINT bit in TWCR to start transmission of data Wait for TWINT flag set. This indicates that the DATA has been transmitted, and ACK/NACK has been received. Check value of TWI Status Register. Mask prescaler bits. If status different from MT_DATA_ACK go to ERROR Transmit STOP condition
3
in cpi ldi out ldi out in
r16,TWSR r16, START r16, SLA_W TWDR, r16 r16, (1<if ((TWSR & 0xF8) != START) ERROR();
andi r16, 0xF8 brne ERROR
4
TWDR = SLA_W; TWCR = (1<wait2: r16,TWCR sbrs r16,TWINT rjmp wait2
while (!(TWCR & (1<5
in cpi ldi out ldi out
r16,TWSR r16, MT_SLA_ACK r16, DATA TWDR, r16 r16, (1<if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR();
andi r16, 0xF8 brne ERROR
TWDR = DATA; TWCR = (1<6
wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3
while (!(TWCR & (1<7
in cpi ldi out
r16,TWSR r16, MT_DATA_ACK r16, (1<if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR();
andi r16, 0xF8 brne ERROR
TWCR = (1<Note:
1. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
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Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used. It is the application software that decides which modes are legal. The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations: S: Rs: R: W: A: A: Data: P: SLA: START condition REPEATED START condition Read bit (high level at SDA) Write bit (low level at SDA) Acknowledge bit (low level at SDA) Not acknowledge bit (high level at SDA) 8-bit data byte STOP condition Slave Address
In Figure 97 to Figure 103, circles are used to indicate that the TWINT flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT flag is cleared by software. When the TWINT flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given in Table 88 to Table 91. Note that the prescaler bits are masked to zero in these tables.
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Master Transmitter Mode
In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 96). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 96. Data Transfer in Master Transmitter Mode
VCC
Device 1
MASTER TRANSMITTER
Device 2
SLAVE RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 88). In order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
When SLA+W have been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes is detailed in Table 88. When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
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This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 88. Status Codes for Master Transmitter Mode
Status Code (TWSR) Prescaler Bits are 0 0x08 0x10 Application Software Response Status of the Two-wire Serial Bus and Two-wire Serial Interface Hardware A START condition has been transmitted A repeated START condition has been transmitted To TWCR To/from TWDR Load SLA+W Load SLA+W or Load SLA+R 0x18 SLA+W has been transmitted; ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action 0x20 SLA+W has been transmitted; NOT ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action 0x28 Data byte has been transmitted; ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action 0x30 Data byte has been transmitted; NOT ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action 0x38 Arbitration lost in SLA+W or data bytes No TWDR action or No TWDR action STA 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STO 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 TWINT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TWEA X X X X X X X X X X X X X X X X X X X X X Next Action Taken by TWI Hardware SLA+W will be transmitted; ACK or NOT ACK will be received SLA+W will be transmitted; ACK or NOT ACK will be received SLA+R will be transmitted; Logic will switch to Master Receiver mode Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Two-wire Serial Bus will be released and not addressed slave mode entered A START condition will be transmitted when the bus becomes free
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Figure 97. Formats and States in the Master Transmitter Mode
MT
Successfull transmission to a slave receiver
S
SLA
W
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$18
$28
RS
SLA
W
$10
Not acknowledge received after the slave address
A
P
R
$20
MR
Not acknowledge received after a data byte
A
P
$30
Arbitration lost in slave address or data byte
A or A
Other master continues
A or A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
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Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a slave transmitter (see Figure 98). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 98. Data Transfer in Master Receiver Mode
VCC
Device 1
MASTER RECEIVER
Device 2
SLAVE TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 88). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in Table 89. Received data can be read from the TWDR Register when the TWINT flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR Value TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
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After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 89. Status Codes for Master Receiver Mode
Status Code (TWSR) Prescaler Bits are 0 0x08 0x10 Application Software Response Status of the Two-wire Serial Bus and Two-wire Serial Interface Hardware A START condition has been transmitted A repeated START condition has been transmitted To TWCR To/from TWDR Load SLA+R Load SLA+R or Load SLA+W 0x38 Arbitration lost in SLA+R or NOT ACK bit No TWDR action or No TWDR action 0x40 SLA+R has been transmitted; ACK has been received SLA+R has been transmitted; NOT ACK has been received No TWDR action or No TWDR action 0x48 No TWDR action or No TWDR action or No TWDR action 0x50 Data byte has been received; ACK has been returned Data byte has been received; NOT ACK has been returned Read data byte or Read data byte 0x58 Read data byte or Read data byte or Read data byte STA 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 STO 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 TWINT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TWEA X X X X X 0 1 X X X 0 1 X X X Next Action Taken by TWI Hardware SLA+R will be transmitted ACK or NOT ACK will be received SLA+R will be transmitted ACK or NOT ACK will be received SLA+W will be transmitted Logic will switch to Master Transmitter mode Two-wire Serial Bus will be released and not addressed Slave mode will be entered A START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset
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Figure 99. Formats and States in the Master Receiver Mode
MR
Successfull reception from a slave receiver
S
SLA
R
A
DATA
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$40
$50
$58
RS
SLA
R
$10
Not acknowledge received after the slave address
A
P
W
$48
MT
Arbitration lost in slave address or data byte
A or A
Other master continues
A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
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Slave Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see Figure 100). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 100. Data Transfer in Slave Receiver Mode
VCC
Device 1
SLAVE RECEIVER
Device 2
MASTER TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR Value TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device's Own Slave Address
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
TWCR Value TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device's own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is "0" (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 90. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and 0x78). If the TWEA bit is reset during a transfer, the TWI will return a "Not Acknowledge" ("1") to SDA after the next received data byte. This can be used to indicate that the slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake-up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data reception will be car220
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ried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register - TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. Table 90. Status Codes for Slave Receiver Mode
Status Code (TWSR) Prescaler Bits Are 0 0x60 Application Software Response Status of the Two-wire Serial Bus and Two-wire Serial Interface Hardware Own SLA+W has been received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been received; ACK has been returned General call address has been received; ACK has been returned Arbitration lost in SLA+R/W as master; General call address has been received; ACK has been returned Previously addressed with own SLA+W; data has been received; ACK has been returned Previously addressed with own SLA+W; data has been received; NOT ACK has been returned To TWCR To/from TWDR No TWDR action or No TWDR action 0x68 No TWDR action or No TWDR action No TWDR action or No TWDR action 0x78 No TWDR action or No TWDR action Read data byte or Read data byte Read data byte or Read data byte or STA X X X X X X X X X X 0 0 STO 0 0 0 0 0 0 0 0 0 0 0 0 TWINT 1 1 1 1 1 1 1 1 1 1 1 1 TWEA 0 1 0 1 0 1 0 1 0 1 0 1 Next Action Taken by TWI Hardware Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free
0x70
0x80
0x88
Read data byte or
1
0
1
0
Read data byte
1
0
1
1
0x90
Previously addressed with general call; data has been received; ACK has been returned Previously addressed with general call; data has been received; NOT ACK has been returned
Read data byte or Read data byte Read data byte or Read data byte or
X X 0 0
0 0 0 0
1 1 1 1
0 1 0 1
0x98
Read data byte or
1
0
1
0
Read data byte
1
0
1
1
0xA0
A STOP condition or repeated START condition has been received while still addressed as slave
No Action
0 0
0 0
1 1
0 1
1
0
1
0
1
0
1
1
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Figure 101. Formats and States in the Slave Receiver Mode
Reception of the own slave address and one or more data bytes. All are acknowledged
S
SLA
W
A
DATA
A
DATA
A
P or S
$60
Last data byte received is not acknowledged
$80
$80
$A0
A
P or S
$88
Arbitration lost as master and addressed as slave
A
$68
Reception of the general call address and one or more data bytes
General Call
A
DATA
A
DATA
A
P or S
$70
Last data byte received is not acknowledged
$90
$90
$A0
A
P or S
$98
Arbitration lost as master and addressed as slave by general call
A
$78
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
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Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 102). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 102. Data Transfer in Slave Transmitter Mode
VCC
Device 1
SLAVE TRANSMITTER
Device 2
MASTER RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR Value TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device's Own Slave Address
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
TWCR Value TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device's own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is "1" (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 91. The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master mode (see state 0xB0). If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the master receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave mode, and will ignore the master if it continues the transfer. Thus the master receiver receives all "1" as serial data. State 0xC8 is entered if the master demands additional data bytes (by transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expecting NACK from the master). While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. 223
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In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register - TWDR - does not reflect the last byte present on the bus when waking up from these sleep modes. Table 91. Status Codes for Slave Transmitter Mode
Status Code (TWSR) Prescaler Bits are 0 0xA8 Application Software Response Status of the Two-wire Serial Bus and Two-wire Serial Interface Hardware Own SLA+R has been received; ACK has been returned To TWCR To/from TWDR Load data byte or Load data byte 0xB0 Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned Data byte in TWDR has been transmitted; ACK has been received Data byte in TWDR has been transmitted; NOT ACK has been received Load data byte or Load data byte Load data byte or Load data byte No TWDR action or No TWDR action or STA X X X X X X 0 0 STO 0 0 0 0 0 0 0 0 TWINT 1 1 1 1 1 1 1 1 TWEA 0 1 0 1 0 1 0 1 Next Action Taken by TWI Hardware Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free
0xB8
0xC0
No TWDR action or
1
0
1
0
No TWDR action
1
0
1
1
0xC8
Last data byte in TWDR has been transmitted (TWEA = "0"); ACK has been received
No TWDR action or No TWDR action or
0 0
0 0
1 1
0 1
No TWDR action or
1
0
1
0
No TWDR action
1
0
1
1
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Figure 103. Formats and States in the Slave Transmitter Mode
Reception of the own slave address and one or more data bytes
S
SLA
R
A
DATA
A
DATA
A
P or S
$A8
Arbitration lost as master and addressed as slave
$B8
$C0
A
$B0
Last data byte transmitted. Switched to not addressed slave (TWEA = '0')
A
All 1's
P or S
$C8
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 92. Status 0xF8 indicates that no relevant information is available because the TWINT flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.
Table 92. Miscellaneous States
Status Code (TWSR) Prescaler Bits are 0 0xF8 0x00 Application Software Response Status of the Two-wire Serial Bus and Two-wire Serial Interface hardware No relevant state information available; TWINT = "0" Bus error due to an illegal START or STOP condition To TWCR To/from TWDR No TWDR action No TWDR action 0 STA STO TWINT TWEA Next Action Taken by TWI Hardware Wait or proceed current transfer X Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and TWSTO is cleared.
No TWCR action 1 1
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Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2. The EEPROM must be instructed what location should be read. 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomic operation. If this principle is violated in a multimaster system, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the master keeps ownership of the bus. The following figure shows the flow in this transfer. Figure 104. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter Master Receiver
S
SLA+W
A
ADDRESS
A
Rs
SLA+R
A
DATA
A
P
S = START Transmitted from master to slave
Rs = REPEATED START Transmitted from slave to master
P = STOP
Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. Figure 105. An Arbitration Example
VCC
Device 1
MASTER TRANSMITTER
Device 2
MASTER TRANSMITTER
Device 3
SLAVE RECEIVER
........
Device n
R1
R2
SDA
SCL
Several different scenarios may arise during arbitration, as described below: 226
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* Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the masters will know about the bus contention. Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action.
*
*
This is summarized in Figure 106. Possible status values are given in circles. Figure 106. Possible Status Codes Caused by Arbitration
START SLA Data STOP
Arbitration lost in SLA
Arbitration lost in Data
Own Address / General Call received
No
38
TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free
Yes Write 68/78
Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned
Direction
Read B0
Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received
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Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator's output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 107. Figure 107. Analog Comparator Block Diagram(1)(2)
BANDGAP REFERENCE ACBG
ACME ADEN ADC MULTIPLEXER OUTPUT 1)
Notes:
1. See Table 94 on page 230. 2. Refer to Figure 1 on page 2 and Table 30 on page 74 for Analog Comparator pin placement.
SFIOR - Special Function IO Register
Bit 0x20 (0x40) Read/Write Initial Value
7 TSM R/W 0
6 - R 0
5 - R 0
4 - R 0
3 ACME R/W 0
2 PUD R/W 0
1 PSR2 R/W 0
0 PSR10 R/W 0 SFIOR
* Bit 3 - ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see "Analog Comparator Multiplexed Input" on page 230.
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ACSR - Analog Comparator Control and Status Register
Bit 0x08 (0x28) Read/Write Initial Value 7 ACD R/W 0 6 ACBG R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR
* Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See "Internal Voltage Reference" on page 56. * Bit 5 - ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. * Bit 2 - ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.
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* Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 93. Table 93. ACIS1/ACIS0 Settings
ACIS1 0 0 1 1 ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle. Reserved Comparator Interrupt on Falling Output Edge. Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
Analog Comparator Multiplexed Input
It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 94. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 94. Analog Comparator Multiplexed Input
ACME 0 1 1 1 1 1 1 1 1 1 ADEN x 1 0 0 0 0 0 0 0 0 MUX2..0 xxx xxx 000 001 010 011 100 101 110 111 Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
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Analog to Digital Converter
Features
* * * * * * * * * * * * * * * *
10-bit Resolution 0.75 LSB Integral Non-linearity 1.5 LSB Absolute Accuracy 13 - 260 s Conversion Time Up to 15 kSPS at Maximum Resolution Eight Multiplexed Single Ended Input Channels Seven Differential Input Channels Two Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.7 - VCC Differential ADC Voltage Range Selectable 2.56V ADC Reference Voltage Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler
The ATmega64 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND). The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog input channels share a common negative terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be expected. The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 108. The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than 0.3V from VCC. See the paragraph "ADC Noise Canceler" on page 239 on how to connect this pin. Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance.
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Figure 108. Analog to Digital Converter Block Schematic
ADC CONVERSION COMPLETE IRQ
INTERRUPT FLAGS ADTS[2:0]
8-BIT DATA BUS
ADIF ADIE
15 ADC DATA REGISTER (ADCH/ADCL)
ADPS0 ADC[9:0]
0
ADC MULTIPLEXER SELECT (ADMUX)
MUX3 MUX1 REFS1 ADLAR REFS0 MUX4 MUX2 MUX0
ADC CTRL. & STATUS REGISTER (ADCSRA)
ADATE ADPS2 ADPS1 ADEN
ADSC
ADIF
TRIGGER SELECT MUX DECODER
CHANNEL SELECTION
PRESCALER
GAIN SELECTION
START
CONVERSION LOGIC
AVCC
INTERNAL 2.56V REFERENCE AREF
10-BIT DAC
SAMPLE & HOLD COMPARATOR +
GND
BANDGAP REFERENCE
ADC7
SINGLE ENDED / DIFFERENTIAL SELECTION
ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 + POS. INPUT MUX
ADC MULTIPLEXER OUTPUT
GAIN AMPLIFIER
NEG. INPUT MUX
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential gain amplifier. If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
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The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event.
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Figure 109. ADC Auto Trigger Logic
ADTS[2:0] PRESCALER
START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE
CLKADC
CONVERSION LOGIC EDGE DETECTOR
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started.
Prescaling and Conversion Timing
Figure 110. ADC Prescaler
ADEN START CK Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
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CK/128
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
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The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See "Differential Gain Channels" on page 237 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of a first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. When using Differential mode, along with auto trigging from a source other that the ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 95. Figure 111. ADC Timing Diagram, First Conversion (Single Conversion Mode)
First Conversion Next Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock ADEN ADSC ADIF ADCH ADCL MSB of Result LSB of Result
MUX and REFS Update
Sample & Hold
Conversion Complete
MUX and REFS Update
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Figure 112. ADC Timing Diagram, Single Conversion
One Conversion Next Conversion
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
Figure 113. ADC Timing Diagram, Auto Triggered Conversion
One Conversion Next Conversion
Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset
Prescaler Reset
Figure 114. ADC Timing Diagram, Free Running Conversion
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
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Table 95. ADC Conversion Time
Condition First conversion Normal conversions, single ended Auto Triggered conversions Normal conversions, differential Sample & Hold (Cycles from Start of Conversion) 13.5 1.5 2 1.5/2.5 Conversion Time (Cycles) 25 13 13.5 13/14
Differential Gain Channels
When using differential gain channels, certain aspects of the conversion need to be taken into consideration. Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific phase of CKADC2. A conversion initiated by the user (i.e., all single conversions, and the first free running conversion) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initiated immediately after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock cycles. The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may be subjected to non-linear amplification. An external low-pass filter should be used if the input signal contains higher frequency components than the gain stage bandwidth. Note that the ADC clock frequency is independent of the gain stage bandwidth limitation. For example, the ADC clock period may be 6 s, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this channel. If differential gain channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started. Since the gain stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to "0" then to "1"), only extended conversions are performed. The result from the extended conversions will be valid. See "Prescaling and Conversion Timing" on page 234 for timing details.
Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
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If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1. When ADATE or ADEN is cleared. 2. During conversion, minimum one ADC clock cycle after the trigger event. 3. After a conversion, before the interrupt flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 s to stabilize to the new value. Thus conversions should not be started within the first 125 s after selecting a new differential channel. Alternatively, conversion results obtained within this period should be discarded. The same settling time should be observed for the first differential conversion after changing ADC reference (by changing the REFS1:0 bits in ADMUX). If the JTAG interface is enabled, the function of ADC channels on PORTF7:4 is overridden. Refer to Table 42, "Port F Pins Alternate Functions," on page 83. ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. When switching to a differential gain channel, the first conversion result may have a poor accuracy due to the required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first conversion result. ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high impedant source, and only a capacitive load should be connected in a system. If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch
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between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 136 on page 335.
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. 2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. 3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in Active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. If the ADC is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result.
Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 115. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. If differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred k or less is recommended. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC.
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Figure 115. Analog Input Circuitry
IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2
Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks. 2. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 116. 3. Use the ADC noise canceler function to reduce induced noise from the CPU. 4. If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. Figure 116. ADC Power Connections
(AD0) PA0 VCC GND (ADC7) PF7 (ADC6) PF6 (ADC5) PF5 (ADC4) PF4 (ADC3) PF3 (ADC2) PF2 (ADC1) PF1 (ADC0) PF0
10
51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
AREF GND AVCC
100 nF
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PEN
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Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB. An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n - 1. Several parameters describe the deviation from the ideal behavior: * Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB.
ADC Accuracy Definitions
Figure 117. Offset Error
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
*
Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB
Figure 118. Gain Error
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
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*
Integral Non-linearity (INL): After adjusting for Offset and Gain Error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
Figure 119. Integral Non-linearity (INL)
Output Code
INL
Ideal ADC Actual ADC
VREF
Input Voltage
*
Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
Figure 120. Differential Non-linearity (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
*
Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB. Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of Offset, Gain Error, Differential Error, Non-linearity, and Quantization Error. Ideal value: 0.5 LSB.
*
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ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result registers (ADCL, ADCH). For single ended conversion, the result is V IN 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 97 on page 244 and Table 98 on page 245). 0x000 represents ground, and 0x3FF represents the selected reference voltage minus one LSB. If differential channels are used, the result is ( V POS - V NEG ) GAIN 512 ADC = ----------------------------------------------------------------------V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, GAIN the selected gain factor, and VREF the selected voltage reference. The result is presented in two's complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user wants to perform a quick polarity check of the results, it is sufficient to read the MSB of the result (ADC9 in ADCH). If this bit is one, the result is negative, and if this bit is zero, the result is positive. Figure 121 shows the decoding of the differential input range. Table 96 shows the resulting output codes if the differential input channel pair (ADCn ADCm) is selected with a gain of GAIN and a reference voltage of VREF. Figure 121. Differential Measurement Range
Output Code 0x1FF
0x000 - V REF/GAIN 0x3FF 0 VREF/GAIN Differential Input Voltage (Volts)
0x200
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Table 96. Correlation Between Input Voltage and Output Codes
VADCn VADCm + VREF/GAIN VADCm + 511/512 VREF/GAIN VADCm + 510/512 VREF/GAIN ... VADCm + 1/512 VREF/GAIN VADCm VADCm - 1/512 VREF/GAIN ... VADCm - 511/512VREF/GAIN VADCm - VREF/GAIN Read Code 0x1FF 0x1FF 0x1FE ... 0x001 0x000 0x3FF ... 0x201 0x200 Corresponding Decimal Value 511 511 510 ... 1 0 -1 ... -511 -512
Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result). Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270. ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. ADMUX - ADC Multiplexer Selection Register
Bit 0x07 (0x27) Read/Write Initial Value
7 REFS1 R/W 0
6 REFS0 R/W 0
5 ADLAR R/W 0
4 MUX4 R/W 0
3 MUX3 R/W 0
2 MUX2 R/W 0
1 MUX1 R/W 0
0 MUX0 R/W 0 ADMUX
* Bit 7:6 - REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 97. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Table 97. Voltage Reference Selections for ADC
REFS1 0 0 1 1 REFS0 0 1 0 1 Voltage Reference Selection AREF, Internal Vref turned off. AVCC with external capacitor at AREF pin. Reserved Internal 2.56V Voltage Reference with external capacitor at AREF pin.
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* Bit 5 - ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see "ADCL and ADCH - The ADC Data Register" on page 247. * Bits 4:0 - MUX4:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 98 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 98. Input Channel and Gain Selections
MUX4..0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 N/A Single Ended Input ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC0 ADC1 ADC2 ADC3 ADC2 ADC3 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC0 ADC0 ADC0 ADC0 ADC2 ADC2 ADC2 ADC2 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC2 ADC2 10x 10x 200x 200x 10x 10x 200x 200x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x N/A Positive Differential Input Negative Differential Input Gain
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Table 98. Input Channel and Gain Selections (Continued)
MUX4..0 11010 11011 11100 11101 11110 11111 1.22V (VBG) 0V (GND) Single Ended Input Positive Differential Input ADC2 ADC3 ADC4 ADC5 N/A Negative Differential Input ADC2 ADC2 ADC2 ADC2 Gain 1x 1x 1x 1x
ADCSRA - ADC Control and Status Register A
Bit 0x06 (0x26) Read/Write Initial Value
7 ADEN R/W 0
6 ADSC R/W 0
5 ADATE R/W 0
4 ADIF R/W 0
3 ADIE R/W 0
2 ADPS2 R/W 0
1 ADPS1 R/W 0
0 ADPS0 R/W 0 ADCSRA
* Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. * Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. * Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.
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* Bits 2:0 - ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 99. ADC Prescaler Selections
ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 Division Factor 2 2 4 8 16 32 64 128
ADCL and ADCH - The ADC Data Register ADLAR = 0
Bit 0x05 (0x25) 0x04 (0x24) 15 - ADC7 7 Read/Write R R Initial Value 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
ADLAR = 1
Bit 0x05 (0x25) 0x04 (0x24) 15 ADC9 ADC1 7 Read/Write R R Initial Value 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL
When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two's complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
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* ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in "ADC Conversion Result" on page 243. ADCSRB - ADC Control and Status Register B
Bit (0x8E) Read/Write Initial Value
7 - R 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 ADTS2 R/W 0
1 ADTS1 R/W 0
0 ADTS0 R/W 0 ADCSRB
* Bits 7:3 - Res: Reserved Bits These bits are reserved bits in the ATmega64 and will always read as zero. * Bit 2:0 - ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Figure 122. ADC Auto Trigger Source Selections
ADTS2 0 0 0 0 1 1 1 1 ADTS1 0 0 1 1 0 0 1 1 ADTS0 0 1 0 1 0 1 0 1 Trigger Source Free Running mode Analog Comparator External Interrupt Request 0 Timer/Counter0 Compare Match Timer/Counter0 Overflow Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter1 Capture Event
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JTAG Interface and On-chip Debug System
Features
* JTAG (IEEE std. 1149.1 Compliant) Interface * Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard * Debugger Access to:
- All Internal Peripheral Units - Internal and External RAM - The Internal Register File - Program Counter - EEPROM and Flash Memories * Extensive On-chip Debug Support for Break Conditions, Including - AVR Break Instruction - Break on Change of Program Memory Flow - Single Step Break - Program Memory Break Points on Single Address or Address Range - Data Memory Break Points on Single Address or Address Range * Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface * On-chip Debugging Supported by AVR Studio(R)
Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for: * * * Testing PCBs by using the JTAG Boundary-scan capability. Programming the non-volatile memories, Fuses and Lock bits. On-chip debugging.
A brief description is given in the following sections. Detailed descriptions for Programming via the JTAG interface, and using the Boundary-scan chain can be found in the sections "Programming Via the JTAG Interface" on page 313 and "IEEE 1149.1 (JTAG) Boundary-scan" on page 255, respectively. The On-chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Figure 123 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several data registers as the scan chain (Shift Register) between the TDI - input and TDO - output. The Instruction Register holds JTAG instructions controlling the behavior of a data register. The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registers used for board-level testing. The JTAG Programming Interface (actually consisting of several physical and virtual data registers) is used for serial programming via the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
TAP - Test Access Port
The JTAG interface is accessed through four of the AVR's pins. In JTAG terminology, these pins constitute the Test Access Port - TAP. These pins are: * * * * TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. TCK: Test clock. JTAG operation is synchronous to TCK. TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). TDO: Test Data Out. Serial output data from Instruction Register or Data Register. 249
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The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The device is shipped with this fuse programmed. For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debugger to be able to detect External Reset sources. The debugger can also pull the RESET pin low to reset the whole system, assuming only open collectors on the reset line are used in the application. Figure 123. Block Diagram
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI TDO TCK TMS
TAP CONTROLLER
JTAG PROGRAMMING INTERFACE
AVR CPU INSTRUCTION REGISTER ID REGISTER M U X BYPASS REGISTER FLASH MEMORY Address Data INTERNAL SCAN CHAIN PC Instruction
BREAKPOINT UNIT
DIGITAL PERIPHERAL UNITS
ANALOG PERIPHERIAL UNITS
BREAKPOINT SCAN CHAIN ADDRESS DECODER JTAG / AVR CORE COMMUNICATION INTERFACE
OCD STATUS AND CONTROL
I/O PORT n
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Control & Clock lines
Analog inputs
FLOW CONTROL UNIT
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Figure 124. TAP Controller State Diagram
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 124 depends on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-Logic-Reset. As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers. Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is: * At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register - Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in from the TDI 251
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pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected data register. * Apply the TMS sequence 1, 1, 0 to reenter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register - Shift-DR state. While in this state, upload the selected data register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high. While the data register is shifted in from the TDI pin, the parallel inputs to the data register captured in the Capture-DR state is shifted out on the TDO pin. Apply the TMS sequence 1, 1, 0 to reenter the Run-Test/Idle state. If the selected data register has a latched parallel-output, the latching takes place in the UpdateDR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
*
*
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using data registers, and some JTAG instructions may select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for five TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in "Bibliography" on page 254.
Using the Boundary scan Chain
A complete description of the Boundary-scan capabilities are given in the section "IEEE 1149.1 (JTAG) Boundary-scan" on page 255.
Using the On-chip Debug As shown in Figure 123, the hardware support for On-chip Debugging consists mainly of: system
* * * A scan chain on the interface between the internal AVR CPU and the internal peripheral units. Break Point unit. Communication interface between the CPU and JTAG system.
All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part of the communication interface between the CPU and the JTAG system. The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two Program Memory Break Points, and two combined Break Points. Together, the four Break Points can be configured as either: * * * 4 Single Program Memory Break Points. 3 Single Program Memory Break Points + 1 Single Data Memory Break Point. 2 Single Program Memory Break Points + 2 Single Data Memory Break Points.
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* * 2 Single Program Memory Break Points + 1 Program Memory Break Point with mask ("range Break Point"). 2 Single Program Memory Break Points + 1 Data Memory Break Point with mask ("range Break Point").
A debugger, like the AVR Studio(R), may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in "On-chip Debug Specific JTAG Instructions" on page 253. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the Onchip Debug system to work. As a security feature, the On-chip Debug system is disabled when any Lock bits are set. Otherwise, the On-chip Debug system would have provided a back-door into a secured device. The AVR Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. AVR Studio supports source level execution of Assembly programs assembled with Atmel AVR Assembler and C programs compiled with third party vendors' compilers. AVR Studio runs under Microsoft(R) Windows(R) 95/98/2000/XP/NT(R). For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only highlights are presented in this document. All necessary execution commands are available in AVR Studio, both on source level and on disassembly level. The user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. In addition, the user can have an unlimited number of code Break Points (using the BREAK instruction) and up to two data memory Break Points, alternatively combined as a mask (range) Break Point.
On-chip Debug Specific JTAG Instructions
PRIVATE0; 0x8 PRIVATE1; 0x9 PRIVATE2; 0xA PRIVATE3; 0xB
The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference. Private JTAG instruction for accessing On-chip Debug system. Private JTAG instruction for accessing On-chip Debug system. Private JTAG instruction for accessing On-chip Debug system. Private JTAG instruction for accessing On-chip Debug system.
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On-chip Debug Related Register in I/O Memory
OCDR - On-chip Debug Register
Bit 0x22 (0x42) Read/Write Initial Value 7 MSB/IDRD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 OCDR
The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Register Dirty - IDRD - is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables access to the OCDR Register. In all other cases, the standard I/O location is accessed. Refer to the debugger documentation for further information on how to use this register.
Using the JTAG Programming Capabilities
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse must be programmed and the JTD bit in the MCUSR Register must be cleared to enable the JTAG Test Access Port. The JTAG programming capability supports: * * * * Flash Programming and verifying EEPROM Programming and verifying Fuse Programming and verifying Lock bit Programming and verifying
The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a Chip Erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device. The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section "Programming Via the JTAG Interface" on page 313.
Bibliography
For more information about general Boundary-scan, the following literature can be consulted: * * IEEE: IEEE Std 1149.1 - 1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993. Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison - Wesley, 1992.
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IEEE 1149.1 (JTAG) Boundary-scan
Features
* * * * *
JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Full Scan of all Port Functions as well as Analog Circuitry Having Off-chip Connections Supports the Optional IDCODE Instruction Additional Public AVR_RESET Instruction to Reset the AVR
System Overview
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, Boundary-scan provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the four TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the printed circuit board. Initial scanning of the data register path will show the ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. Entering reset, the outputs of any Port Pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSR must be cleared to enable the JTAG Test Access Port. When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal chip frequency is possible. The chip clock is not required to run.
Data Registers
The data registers relevant for Boundary-scan operations are: * * * * Bypass Register Device Identification Register Reset Register Boundary-scan Chain
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Bypass Register
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. Figure 125 shows the structure of the Device Identification Register. Figure 125. The Format of the Device Identification Register
MSB
Bit Device ID LSB
Device Identification Register
31
4 bits
28
27
16 bits
12
11
Manufacturer ID 11 bits
1
0
1 1-bit
Version
Part Number
Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on. The part number is a 16-bit code identifying the component. The JTAG Part Number for ATmega64 is listed in Table 100. Table 100. AVR JTAG Part Number
Part Number ATmega64 JTAG Part Number (Hex) 0x9602
Part Number
Manufacturer ID
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for Atmel is listed in Table 101. Table 101. Manufacturer ID
Manufacturer Atmel JTAG Man. ID (Hex) 0x01F
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Reset Register The Reset Register is a Test Data Register used to reset the part. Since the AVR tristates port pins when reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ. A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out Period (refer to "Clock Sources" on page 38) after releasing the Reset Register. The output from this data register is not latched, so the reset will take place immediately, as shown in Figure 126. Figure 126. Reset Register
To TDO
From Other Internal and External Reset Sources From TDI Internal Reset
D
Q
ClockDR * AVR_RESET
Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. See "Boundary-scan Chain" on page 259 for a complete description.
Boundary-scan Specific JTAG Instructions
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not implemented, but all outputs with tri-state capability can be set in highimpedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state. As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction.
EXTEST; 0x0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For analog circuits having Off-chip connections, the interface between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-scan Chain is driven out as soon as the JTAG IR-Register is loaded with the EXTEST instruction.
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The active states are: * * * IDCODE; 0x1 Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. Shift-DR: The internal scan chain is shifted by the TCK input. Update-DR: Data from the scan chain is applied to output pins.
Optional JTAG instruction selecting the 32-bit ID-Register as data register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after Power-up. The active states are: * * Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. Shift-DR: The IDCODE scan chain is shifted by the TCK input.
SAMPLE_PRELOAD; 0x2
Mandatory JTAG instruction for taking a snap-shot of the input/output pins without affecting the system operation, and pre-loading the output latches. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as data register. The active states are: * * * Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. Shift-DR: The Boundary-scan Chain is shifted by the TCK input. Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output latches are not connected to the pins.
AVR_RESET; 0xC
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as data register. Note that the reset will be active as long as there is a logic "one" in the Reset Chain. The output from this chain is not latched. The active states are: * Shift-DR: The Reset Register is shifted by the TCK input.
BYPASS; 0xF
Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states are: * * Capture-DR: Loads a logic "0" into the Bypass Register. Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
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Boundary-scan Related Register in I/O Memory
MCUCSR - MCU Control and Status Register The MCU Control and Status Register contains control bits for general MCU functions, and provides information on which reset source caused an MCU Reset.
Bit 0x34 (0x54) Read/Write Initial Value 7 JTD R/W 0 6 - R 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W See Bit Description 1 EXTRF R/W 0 PORF R/W MCUCSR
* Bit 7 - JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The reason for this is to avoid static current at the TDO pin in the JTAG interface. * Bit 4 - JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset, or by writing a logic zero to the flag.
Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connection. Figure 127 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable - PUExn - function, and a bi-directional pin cell that combines the three signals, Output Control - OCxn, Output Data - ODxn, and Input Data - IDxn, into only a two-stage Shift Register. The port and pin indexes are not used in the following description. The Boundary-scan logic is not included in the figures in this Datasheet. Figure 128 shows a simple digital Port Pin as described in the section "I/O Ports" on page 66. The Boundary-scan details from Figure 127 replaces the dashed box in Figure 128. When no alternate port function is present, the Input Data - ID corresponds to the PINxn Register value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction - DD Register, and the Pullup Enable - PUExn - corresponds to logic expression PUD * DDxn * PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 128 to make the scan chain read the actual pin value. For analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry.
Scanning the Digital Port Pins
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Figure 127. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function
ShiftDR
Pullup Enable (PUE)
To Next Cell
EXTEST
Vcc
0 FF2 0 D 1 G Q D Q LD2 1
Output Control (OC)
FF1 0 D 1 Q
LD1 D G Q
0 1
Output Data (OD)
0 1 0
FF0 D 1 Q
LD0 D G Q
0 1
Input Data (ID)
From Last Cell
ClockDR
UpdateDR
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Port Pin (PXn)
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Figure 128. General Port Pin Schematic Diagram
See Boundary-scan Description for Details!
PUExn
PUD
Q
D
DDxn
Q CLR
OCxn
RESET
WDx
RDx
Pxn
Q
D
ODxn IDxn SLEEP
PORTxn
Q CLR
WPx RESET RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn
L
Q
Q
CLK I/O
PUD: PUExn: OCxn: ODxn: IDxn: SLEEP:
PULLUP DISABLE PULLUP ENABLE for pin Pxn OUTPUT CONTROL for pin Pxn OUTPUT DATA to pin Pxn INPUT DATA from pin Pxn SLEEP CONTROL
WDx: RDx: WPx: RRx: RPx: CLK I/O :
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN I/O CLOCK
Boundary-scan and the Twowire Interface
The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-chain; Two-wire Interface Enable - TWIEN. As shown in Figure 129, the TWIEN signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general scan cell as shown in Figure 133 is attached to the TWIEN signal.
Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-scan. 2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention.
DATA BUS
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Figure 129. Additional Scan Signal for the Two-wire Interface
PUExn
OCxn
ODxn
Pxn
TWIEN
SRC
Slew-rate limited IDxn
Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 130 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV. Figure 130. Observe-only Cell
From System Pin
FF1
0 D 1 Q
From Previous Cell
ClockDR
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To System Logic
ShiftDR
To Next Cell
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Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 131 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections. Figure 131. Boundary-scan Cells for Oscillators and Clock Options
XTAL1/TOSC1 XTAL2/TOSC2
From Digital Logic
ShiftDR
To Next Cell
EXTEST
Oscillator
ENABLE OUTPUT
0 1 0 D 1 G Q D Q 0 D 1 Q
FF1
From Previous Cell
ClockDR
UpdateDR From Previous Cell ClockDR
Table 102 summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator. Table 102. Scan Signals for the Oscillators(1)(2)(3)
Enable Signal EXTCLKEN OSCON RCOSCEN OSC32EN TOSKON Notes: Scanned Clock Line EXTCLK (XTAL1) OSCCK RCCK OSC32CK TOSCK Clock Option External Clock External Crystal External Ceramic Resonator External RC Low Freq. External Crystal 32 kHz Timer Oscillator Scanned Clock Line when Not Used 0 0 0 1 0
1. Do not enable more than one clock source as main clock at a time. 2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is preferred. 3. The clock configuration is programmed by fuses. As a fuse does not change run-time, the clock configuration is considered fixed for a given application. The user is advised to scan the same clock option as to be used in the final system. The enable signals are supported in the scan chain because the system logic can disable clock options
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To System Logic
ShiftDR
To Next Cell
in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not provided. The INTCAP Fuses are not supported in the scan-chain, so the boundary scan chain cannot make a XTAL Oscillator requiring internal capacitors to run unless the fuse is correctly programmed.
Scanning the Analog Comparator
The relevant Comparator signals regarding Boundary-scan are shown in Figure 132. The Boundary-scan cell from Figure 133 is attached to each of these signals. The signals are described in Table 103. The Comparator needs not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 132. Analog Comparator
BANDGAP REFERENCE ACBG
ACO
AC_IDLE
ACME ADCEN ADC MULTIPLEXER OUTPUT
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Figure 133. General Boundary-scan Cell used for Signals for Comparator and ADC
From Digital Logic/ From Analog Ciruitry
ShiftDR
To Next Cell
EXTEST To Analog Circuitry/ To Digital Logic
Output Values when Recommended Inputs are Used Depends upon C code being executed 0 Depends upon C code being executed Depends upon C code being executed
0 1 0 D 1 G Q D Q
From Previous Cell
ClockDR
UpdateDR
Table 103. Boundary-scan Signals for the Analog Comparator
Signal Name AC_IDLE Direction as Seen from the Comparator Input Recommended Input when Not in Use 1
Description Turns off Analog Comparator when true Analog Comparator Output Uses output signal from ADC mux when true Bandgap Reference enable
ACO
Output
Will become input to C code being executed 0
ACME
Input
ACBG
Input
0
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Scanning the ADC
Figure 134 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 130 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 134. Analog to Digital Converter
VCCREN AREF IREFEN
TO COMPARATOR
2.56V Ref
MUXEN_7 ADC_7 MUXEN_6 ADC_6 MUXEN_5 ADC_5 MUXEN_4 ADC_4 EXTCH MUXEN_3 ADC_3 MUXEN_2 ADC_2 MUXEN_1 ADC_1 MUXEN_0 ADC_0 NEGSEL_2 NEGSEL_1 NEGSEL_0
ADC_2 ADC_1 ADC_0
PASSEN
SCTEST
ADCBGEN
1.22V Ref
PRECH AREF DAC_9..0 10-bit DAC
AREF DACOUT
+ -
G10 +
G20 ACTEN +
ADCEN
COMP
10x
-
20x HOLD GNDEN
ST ACLK AMPEN
The signals are described briefly in Table 104.
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Table 104. Boundary-scan Signals for the ADC(1)
Direction as Seen from the ADC Output Input Recommended Input when not in Use 0 0 Output Values when Recommended Inputs are Used, and CPU is not Using the ADC 0 0
Signal Name COMP ACLK
Description Comparator Output Clock signal to gain stages implemented as Switch-cap filters Enable path from gain stages to the Comparator Enable Band-gap reference as negative input to Comparator Power-on signal to the ADC Power-on signal to the gain stages Bit nine of digital value to DAC Bit eight of digital value to DAC Bit seven of digital value to DAC Bit six of digital value to DAC Bit five of digital value to DAC Bit four of digital value to DAC Bit three of digital value to DAC Bit two of digital value to DAC Bit 1 of digital value to DAC Bit 0 of digital value to DAC Connect ADC channels 0 - 3 to bypass path around gain stages Enable 10x gain Enable 20x gain
ACTEN
Input
0
0
ADCBGEN
Input
0
0
ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH
Input Input Input Input Input Input Input Input Input Input Input Input Input
0 0 1 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1
G10 G20
Input Input
0 0
0 0
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Table 104. Boundary-scan Signals for the ADC(1) (Continued)
Direction as Seen from the ADC Input Recommended Input when not in Use 0 Output Values when Recommended Inputs are Used, and CPU is not Using the ADC 0
Signal Name GNDEN
Description Ground the negative input to comparator when true Sample&Hold signal. Sample analog signal when low. Hold signal when high. If gain stages are used, this signal must go active when ACLK is high. Enables Band-gap reference as AREF signal to DAC Input Mux bit 7 Input Mux bit 6 Input Mux bit 5 Input Mux bit 4 Input Mux bit 3 Input Mux bit 2 Input Mux bit 1 Input Mux bit 0 Input Mux for negative input for differential signal, bit 2 Input Mux for negative input for differential signal, bit 1 Input Mux for negative input for differential signal, bit 0 Enable pass-gate of gain stages. Precharge output latch of comparator (Active low)
HOLD
Input
1
1
IREFEN
Input
0
0
MUXEN_7 MUXEN_6 MUXEN_5 MUXEN_4 MUXEN_3 MUXEN_2 MUXEN_1 MUXEN_0 NEGSEL_2
Input Input Input Input Input Input Input Input Input
0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1 0
NEGSEL_1
Input
0
0
NEGSEL_0
Input
0
0
PASSEN PRECH
Input Input
1 1
1 1
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Table 104. Boundary-scan Signals for the ADC(1) (Continued)
Direction as Seen from the ADC Input Recommended Input when not in Use 0 Output Values when Recommended Inputs are Used, and CPU is not Using the ADC 0
Signal Name SCTEST
Description Switch-cap TEST enable. Output from x10 gain stage send out to Port Pin having ADC_4 Output of gain stages will settle faster if this signal is high first two ACLK periods after AMPEN goes high. Selects Vcc as the ACC reference voltage.
ST
Input
0
0
VCCREN
Input
0
0
Note:
1. Incorrect setting of the switches in Figure 134 will make signal contention and may damage the part. There are several input choices to the S&H circuitry on the negative input of the output comparator in Figure 134. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 104 should be used. The user is recommended not to use the Differential Gain stages during scan. Switch-cap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is therefore not provided. The AVR ADC is based on the analog circuitry shown in Figure 134 with a successive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. This can easily be done without running a successive approximation algorithm: apply the lower limit on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high. The ADC needs not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. When using the ADC, remember the following: * * The Port Pin for the ADC channel in use must be configured to be an input with pullup disabled to avoid signal contention. In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before controlling/observing any ADC signal, or perform a dummy conversion before using the first result. The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode).
*
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As an example, consider the task of verifying a 1.5V 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC.
The lower limit is: The upper limit is: 1024 1,5V 0,95 5V = 291 = 0x123 1024 1,5V 1,05 5V = 323 = 0x143
The recommended values from Table 104 are used unless other values are given in the algorithm in Table 105. Only the DAC and Port Pin values of the Scan-chain are shown. The column "Actions" describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table. Table 105. Algorithm for Using the ADC(1)
PA3. Pullup_ Enable 0 0 0 0 0 0 0 0 0 0 0
Ste p 1 2 3 4 5 6 7 8 9 10 11 Note:
Actions SAMPLE_PRELOAD EXTEST
ADCEN 1 1 1 1 1
DAC 0x200 0x200 0x200 0x123 0x123 0x200 0x200 0x200 0x143 0x143 0x200
MUXEN 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08
HOLD 1 0 1 1 1 1 0 1 1 1 1
PRECH 1 1 1 1 0 1 1 1 1 0 1
PA3. Data 0 0 0 0 0 0 0 0 0 0 0
PA3. Control 0 0 0 0 0 0 0 0 0 0 0
Verify the COMP bit scanned out to be 0
1 1 1 1 1
Verify the COMP bit scanned out to be 1
1
1. Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, thold,max.
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ATmega64 Boundaryscan Order
Table 106 shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pinout order as far as possible. Therefore, the bits of Port A are scanned in the opposite bit order of the other ports. Exceptions from the rules are the scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 127, PXn, Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. Table 106. ATmega64 Boundary-scan Order
Bit Number 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 Signal Name AC_IDLE ACO ACME AINBG COMP PRIVATE_SIGNAL1 ACLK ACTEN PRIVATE_SIGNAL2(2) ADCBGEN ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH G10 G20 GNDEN HOLD IREFEN MUXEN_7
(1)
Module Comparator
ADC
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Table 106. ATmega64 Boundary-scan Order (Continued)
Bit Number 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 Signal Name MUXEN_6 MUXEN_5 MUXEN_4 MUXEN_3 MUXEN_2 MUXEN_1 MUXEN_0 NEGSEL_2 NEGSEL_1 NEGSEL_0 PASSEN PRECH SCTEST ST VCCREN PEN PE0.Data PE0.Control PE0.Pullup_Enable PE1.Data PE1.Control PE1.Pullup_Enable PE2.Data PE2.Control PE2.Pullup_Enable PE3.Data PE3.Control PE3.Pullup_Enable PE4.Data PE4.Control PE4.Pullup_Enable PE5.Data PE5.Control PE5.Pullup_Enable PE6.Data PE6.Control Programming Enable (Observe-only) Port E Module ADC
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Table 106. ATmega64 Boundary-scan Order (Continued)
Bit Number 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 Signal Name PE6.Pullup_Enable PE7.Data PE7.Control PE7.Pullup_Enable PB0.Data PB0.Control PB0.Pullup_Enable PB1.Data PB1.Control PB1.Pullup_Enable PB2.Data PB2.Control PB2.Pullup_Enable PB3.Data PB3.Control PB3.Pullup_Enable PB4.Data PB4.Control PB4.Pullup_Enable PB5.Data PB5.Control PB5.Pullup_Enable PB6.Data PB6.Control PB6.Pullup_Enable PB7.Data PB7.Control PB7.Pullup_Enable PG3.Data PG3.Control PG3.Pullup_Enable PG4.Data PG4.Control PG4.Pullup_Enable TOSC TOSCON 32 kHz Timer Oscillator Port G Port B Module Port E
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Table 106. ATmega64 Boundary-scan Order (Continued)
Bit Number 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 Signal Name RSTT RSTHV EXTCLKEN OSCON RCOSCEN OSC32EN EXTCLK (XTAL1) OSCCK RCCK OSC32CK TWIEN PD0.Data PD0.Control PD0.Pullup_Enable PD1.Data PD1.Control PD1.Pullup_Enable PD2.Data PD2.Control PD2.Pullup_Enable PD3.Data PD3.Control PD3.Pullup_Enable PD4.Data PD4.Control PD4.Pullup_Enable PD5.Data PD5.Control PD5.Pullup_Enable PD6.Data PD6.Control PD6.Pullup_Enable PD7.Data PD7.Control PD7.Pullup_Enable PG0.Data Port G TWI Port D Clock Input and Oscillators for the Main Clock (Observe-only) Module Reset Logic (Observe-only) Enable Signals for Main Clock/Oscillators
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Table 106. ATmega64 Boundary-scan Order (Continued)
Bit Number 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Signal Name PG0.Control PG0.Pullup_Enable PG1.Data PG1.Control PG1.Pullup_Enable PC0.Data PC0.Control PC0.Pullup_Enable PC1.Data PC1.Control PC1.Pullup_Enable PC2.Data PC2.Control PC2.Pullup_Enable PC3.Data PC3.Control PC3.Pullup_Enable PC4.Data PC4.Control PC4.Pullup_Enable PC5.Data PC5.Control PC5.Pullup_Enable PC6.Data PC6.Control PC6.Pullup_Enable PC7.Data PC7.Control PC7.Pullup_Enable PG2.Data PG2.Control PG2.Pullup_Enable PA7.Data PA7.Control PA7.Pullup_Enable PA6.Data Port A Port G Port C Module Port G
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Table 106. ATmega64 Boundary-scan Order (Continued)
Bit Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Notes: Signal Name PA6.Control PA6.Pullup_Enable PA5.Data PA5.Control PA5.Pullup_Enable PA4.Data PA4.Control PA4.Pullup_Enable PA3.Data PA3.Control PA3.Pullup_Enable PA2.Data PA2.Control PA2.Pullup_Enable PA1.Data PA1.Control PA1.Pullup_Enable PA0.Data PA0.Control PA0.Pullup_Enable PF3.Data PF3.Control PF3.Pullup_Enable PF2.Data PF2.Control PF2.Pullup_Enable PF1.Data PF1.Control PF1.Pullup_Enable PF0.Data PF0.Control PF0.Pullup_Enable 1. PRIVATE_SIGNAL1 should always scanned in as zero. 2. PRIVATE_SIGNAL2 should always scanned in as zero. Port F Module Port A
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Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description.
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Boot Loader Support - Read-While-Write Self-programming
The Boot Loader Support provides a real Read-While-Write Self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with Fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. * * * * * * *
Read-While-Write Self-programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support 1. A page is a section in the Flash consisting of several bytes (see Table 123 on page 297) used during programming. The page organization does not affect normal operation.
Features
Note:
Application and Boot Loader Flash Sections
The Flash memory is organized in two main sections, the Application section and the Boot Loader section (see Figure 136). The size of the different sections is configured by the BOOTSZ Fuses as shown in Table 112 on page 290 and Figure 136. These two sections can have different levels of protection since they have different sets of Lock bits. The Application section is the section of the Flash that is used for storing the application code. The protection level for the Application section can be selected by the application Boot Lock bits (Boot Lock bits 0), see Table 108 on page 281. The Application section can never store any Boot Loader code since the SPM instruction is disabled when executed from the Application section. While the Application section is used for storing the application code, the Boot Loader software must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 109 on page 281.
Application Section
BLS - Boot Loader Section
Read-While-Write and No Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In Read-While-Write Flash addition to the two sections that are configurable by the BOOTSZ Fuses as described Sections
above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWWand NRWW sections is given in "ATmega64 Boot Loader Parameters" on page 290 and Figure 136 on page 280. The main difference between the two sections is: * * When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation.
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Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax "Read-While-Write section" refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. RWW - Read-While-Write Section If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an ongoing programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader section. The Boot Loader section is always located in the NRWW section. The RWW section Busy Bit (RWWSB) in the Store Program Memory Control Register (SPMCSR) will be read as logical one as long as the RWW section is blocked for reading. After a programming is completed, the RWWSB must be cleared by software before reading code located in the RWW section. See "SPMCSR - Store Program Memory Control Register" on page 282. for details on how to clear RWWSB. The code located in the NRWW section can be read when the Boot Loader software is updating a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU is halted during the entire Page Erase or Page Write operation. Table 107. Read-While-Write Features
Which Section does the Zpointer Address During the Programming? RWW section NRWW section Which Section Can be Read During Programming? NRWW section None Is the CPU Halted? No Yes Read-WhileWrite Supported? Yes No
NRWW - No Read-While-Write Section
Figure 135. Read-While-Write vs. No Read-While-Write
Read-While-Write (RWW) Section
Z-pointer Addresses RWW Section
Z-pointer Addresses NRWW Section
No Read-While-Write (NRWW) Section
CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation
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Figure 136. Memory Sections(1)
Program Memory BOOTSZ = '11' $0000
Read-While-Write Section Read-While-Write Section
Program Memory BOOTSZ = '10' $0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00'
Boot Loader Flash Section
End Application Start Boot Loader Flashend
Program Memory BOOTSZ = '01' $0000
Read-While-Write Section Read-While-Write Section
$0000
Application Flash Section
Application flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend
No Read-While-Write Section
End RWW, End Application Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
Note:
1. The parameters are given in Table 112 on page 290.
Boot Loader Lock Bits
If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: * * * * To protect the entire Flash from a software update by the MCU. To protect only the Boot Loader Flash section from a software update by the MCU. To protect only the Application Flash section from a software update by the MCU. Allow software update in the entire Flash.
See Table 108 and Table 109 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a chip erase command only. The general Write Lock (Lock bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general
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Read/Write Lock (Lock bit mode 3) does not control reading nor writing by LPM/SPM, if it is attempted. Table 108. Boot Lock Bit0 Protection Modes (Application Section)(1)
BLB0 Mode 1 2 3 BLB02 1 1 0 BLB01 1 0 0 Protection No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
4
0
1
Note:
1. "1" means unprogrammed, "0" means programmed
Table 109. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)
BLB1 Mode 1 2 3 BLB12 1 1 0 BLB11 1 0 0 Protection No restrictions for SPM or LPM accessing the Boot Loader section. SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
4
0
1
Note:
1. "1" means unprogrammed, "0" means programmed
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Entering the Boot Loader Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interProgram
face. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 110. Boot Reset Fuse(1)
BOOTRST 1 0 Note: Reset Address Reset Vector = Application Reset (address 0x0000) Reset Vector = Boot Loader Reset (see Table 112 on page 290)
1. "1" means unprogrammed, "0" means programmed
SPMCSR - Store Program Memory Control Register
The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.
Bit (0x68) Read/Write Initial Value 7
SPMIE
6
RWWSB
5
-
4
RWWSRE
3
BLBSET
2
PGWRT
1
PGERS
0
SPMEN SPMCSR
R/W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is cleared. * Bit 6 - RWWSB: Read-While-Write Section Busy When a Self-programming (Page Erase or Page Write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated. * Bit 5 - Res: Reserved Bit This bit is a reserved bit in the ATmega64 and always read as zero. * Bit 4 - RWWSRE: Read-While-Write Section Read Enable When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost.
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* Bit 3 - BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See "Reading the Fuse and Lock Bits from Software" on page 287 for details. * Bit 2 - PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. * Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. * Bit 0 - SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT' or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect.
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Addressing the Flash During Selfprogramming
The Z-pointer is used to address the SPM commands.
Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Since the Flash is organized in pages (see Table 123 on page 297), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 137. Note that the Page Erase and Page Write operations are addressed independently. Therefore, it is of major importance that the Boot Loader software addresses the same page in both the Page Erase and Page Write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (Bit Z0) of the Z-pointer is used. Figure 137. Addressing the Flash during SPM(1)Table 2 on page 284
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Notes:
1. The different variables used in Figure 137 are listed in Table 113 on page 290. 2. PCPAGE and PCWORD are listed in Table 124 on page 297.
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Self-programming the Flash
The program memory is updated in a page-by-page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1, fill the buffer before a Page Erase: * * * * * * Fill temporary page buffer Perform a Page Erase Perform a Page Write Perform a Page Erase Fill temporary page buffer Perform a Page Write
Alternative 2, fill the buffer after Page Erase:
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using Alternative 1, the boot loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If Alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. See "Simple Assembly Code Example for a Boot Loader" on page 288 for an assembly code example. Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write "X0000011" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer must be written zero during this operation. * * Filling the Temporary Buffer (Page Loading) Page Erase to the RWW section: The NRWW section can be read during the Page Erase. Page Erase to the NRWW section: The CPU is halted during the operation.
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in SPMCSR. It is also erased after a System Reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer.
Note: If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write "X0000101" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written zero during this operation. * * Page Write to the RWW section: The NRWW section can be read during the Page Write. Page Write to the NRWW section: The CPU is halted during the operation.
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Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in "Interrupts" on page 61. Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. During Self-programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the Self-programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-programming the Interrupt Vector table should be moved to the BLS as described in "Interrupts" on page 61, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See "Simple Assembly Code Example for a Boot Loader" on page 288 for an example. To set the Boot Loader Lock bits, write the desired data to R0, write "X0001001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
Bit R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1
Consideration While Updating BLS
Prevent Reading the RWW Section During Selfprogramming
Setting the Boot Loader Lock Bits by SPM
See Table 108 and Table 109 for how the different settings of the Boot Loader Bits affect the Flash access. If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don't care during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to "1" when writing the Lock bits. When programming the Lock bits the entire Flash can be read during the operation. EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register.
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Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the AVR Instruction Set Reference Manual.
Bit Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 119 on page 293 for a detailed description and mapping of the Fuse Low bits.
Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below. Refer to Table 118 on page 293 for detailed description and mapping of the Fuse High bits.
Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
When reading the Extended Fuse bits, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse bits (EFB) will be loaded in the destination register as shown below. Refer to Table 117 on page 292 for detailed description and mapping of the Fuse High bits.
Bit Rd 7 - 6 - 5 - 4 - 3 - 2 - 1 EFB1 0 EFB0
Fuse and Lock bits that are programmed will be read as zero. Fuse and Lock bits that are unprogrammed will be read as one. Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Second, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
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1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. Keep the AVR core in Power-down Sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 111 shows the typical programming time for Flash accesses from the CPU. Table 111. SPM Programming Time
Symbol Flash write (Page Erase, Page Write, and write Lock bits by SPM) Min Programming Time 3.7 ms Max Programming Time 4.5 ms
Simple Assembly Code Example for a Boot Loader
;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during self-programming (Page Erase and Page Write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase ldi spmcrval, (1<288
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subi sbci ldi call ZL, low(PAGESIZEB) ;restore pointer ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 spmcrval, (1<; re-enable the RWW section ldi spmcrval, (1<289
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ATmega64 Boot Loader Parameters
In Table 112 through Table 114, the parameters used in the description of the Self-programming are given. Table 112. Boot Size Configuration(1)
Application Flash Section 0x0000 0x7DFF 0x0000 0x7BFF 0x0000 0x77FF 0x0000 0x6FFF Boot Loader Flash Section 0x7E00 0x7FFF 0x7C00 0x7FFF 0x7800 0x7FFF 0x7000 0x7FFF End Application Section 0x7DFF 0x7BFF 0x77FF 0x6FFF Boot Reset Address (Start Boot Loader Section) 0x7E00 0x7C00 0x7800 0x7000
BOOTSZ 1 1 1 0 0 Note:
BOOTSZ 0 1 0 1 0
Boot Size 512 words 1024 words 2048 words 4096 words
Pages 4 8 16 32
1. The different BOOTSZ Fuse configurations are shown in Figure 136
Table 113. Read-While-Write Limit(1)
Section Read-While-Write (RWW) No Read-While-Write (NRWW) Note: Pages 224 32 Address 0x0000 - 0x6FFF 0x7000 - 0x7FFF
1. For details about these two section, see "NRWW - No Read-While-Write Section" on page 279 and "RWW - Read-While-Write Section" on page 279
Table 114. Explanation of Different Variables Used in Figure 137 and the Mapping to the Z-pointer(1)(2)
Variable PCMSB 14 6 PAGEMSB Z15 ZPCMSB Z7 ZPAGEMSB PC[14:7] PC[6:0] PCWORD Notes: Z15:Z8 Z7:Z1 Corresponding Z-value
Description
Most significant bit in the Program Counter. (The Program Counter is 15 bits PC[14:0]). Most significant bit which is used to address the words within one page (128 words in a page requires seven bits PC [6:0]). Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1. Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1. Program Counter page address: Page select, for Page Erase and Page Write Program Counter word address: Word select, for filling temporary buffer (must be zero during Page Write operation)
PCPAGE
1. Z0: should be zero for all SPM commands, byte select for the LPM instruction. 2. See "Addressing the Flash During Self-programming" on page 284 for details about the use of Z-pointer during Self-programming.
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Memory Programming
Program and Data Memory Lock Bits
The ATmega64 provides six Lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 116. The Lock bits can only be erased to "1" with the Chip Erase command. Table 115. Lock Bit Byte(1)
Lock Bit Byte Bit no 7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 Note: 5 4 3 2 1 0 Description - - Boot Lock bit Boot Lock bit Boot Lock bit Boot Lock bit Lock bit Lock bit Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
1. "1" means unprogrammed, "0" means programmed
Table 116. Lock Bit Protection Modes(2)
Memory Lock Bits LB Mode 1 2 LB2 1 1 LB1 1 0 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled in Parallel and SPI/JTAG Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1) Further programming and verification of the Flash and EEPROM is disabled in Parallel and SPI/JTAG Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1) Protection Type
3
0
0
BLB0 Mode 1 2 3
BLB02 1 1 0
BLB01 1 0 0 No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
4
0
1
BLB1 Mode
BLB12
BLB11
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Table 116. Lock Bit Protection Modes(2) (Continued)
Memory Lock Bits 1 2 3 1 1 0 1 0 0 Protection Type No restrictions for SPM or LPM accessing the Boot Loader section. SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
4
0
1
Notes:
1. Program the Fuse bits before programming the Lock bits. 2. "1" means unprogrammed, "0" means programmed
Fuse Bits
The ATmega64 has three fuse bytes. Table 117 - Table 119 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed. Table 117. Extended Fuse Byte
Fuse Low Byte - - - - - - M103C
(1) (2)
Bit no 7 6 5 4 3 2 1 0
Description - - - - - - ATmega103 compatibility mode Watchdog Timer always on
Default Value 1 1 1 1 1 1 0 (programmed) 1 (unprogrammed)
WDTON Notes:
1. See "ATmega103 and ATmega64 Compatibility" on page 4 for details. 2. See "WDTCR - Watchdog Timer Control Register" on page 57 for details.
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Table 118. Fuse High Byte
Fuse High Byte OCDEN JTAGEN(4) SPIEN(1) CKOPT(2) EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes: Bit no 7 6 5 4 3 2 1 0 Description Enable OCD Enable JTAG Enable SPI Serial Program and Data Downloading Oscillator options EEPROM memory is preserved through the Chip Erase Select Boot Size (see Table 112 for details) Select Boot Size (see Table 112 for details) Select Reset Vector Default Value 1 (unprogrammed, OCD disabled) 0 (programmed, JTAG enabled) 0 (programmed, SPI prog. enabled) 1 (unprogrammed) 1 (unprogrammed, EEPROM not preserved) 0 (programmed)(3) 0 (programmed)(3) 1 (unprogrammed)
1. The SPIEN Fuse is not accessible in SPI Serial Programming mode. 2. The CKOPT Fuse functionality depends on the setting of the CKSEL bits. See "Clock Sources" on page 38 for details. 3. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 112 on page 290 4. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This to avoid static current at the TDO pin in the JTAG interface
Table 119. Fuse Low Byte
Fuse Low Byte BODLEVEL BODEN SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: Bit no 7 6 5 4 3 2 1 0 Description Brown out detector trigger level Brown out detector enable Select start-up time Select start-up time Select Clock source Select Clock source Select Clock source Select Clock source Default Value 1 (unprogrammed) 1 (unprogrammed, BOD disabled) 1 (unprogrammed)(1) 0 (programmed)(1) 0 (programmed)(2) 0 (programmed)(2) 0 (programmed)(2) 1 (unprogrammed)(2)
1. The default value of SUT1..0 results in maximum start-up time. See Table 14 on page 43 for details. 2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 1 MHz. See Table 6 on page 38 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
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Latching of Fuses
The fuse values are latched when the device enters Programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. All Atmel microcontrollers have a 3-byte signature code which identifies the device. This code can be read in both Serial and Parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega64 the signature bytes are: 1. 0x000: 0x1E (indicates manufactured by Atmel) 2. 0x001: 0x96 (indicates 64KB Flash memory) 3. 0x002: 0x02 (indicates ATmega64 device when 0x001 is 0x96)
Signature Bytes
Calibration Byte
The ATmega64 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row high byte of the addresses 0x000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded manually, see "OSCCAL - Oscillator Calibration Register(1)" on page 43 for details. This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega64. Pulses are assumed to be at least 250 ns unless otherwise noted.
Parallel Programming Parameters, Pin Mapping, and Commands
Signal Names
In this section, some pins of the ATmega64 are referenced by signal names describing their functionality during parallel programming, see Figure 138 and Table 120. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 122. When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 123.
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Figure 138. Parallel Programming
+5V RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RESET PA0 XTAL1 GND AVCC
PB7 - PB0
VCC +5V
DATA
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Table 120. Pin Name Mapping
Signal Name in Programming Mode RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA Pin Name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PA0 PB7 - 0 I/O O I I I I I I I I/O Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (Active low) Write Pulse (Active low) Byte Select 1 ("0" selects low byte, "1" selects high byte) XTAL Action Bit 0 XTAL Action Bit 1 Program Memory and EEPROM data Page Load Byte Select 2 ("0" selects low byte, "1" selects 2'nd high byte) Bi-directional Data bus (Output when OE is low)
Table 121. Pin Values Used to Enter Programming Mode
Pin PAGEL XA1 XA0 BS1 Symbol Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] Value 0 0 0 0
Table 122. XA1 and XA0 Coding
XA1 0 0 1 1 XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1) Load Data (High or Low data byte for Flash determined by BS1) Load Command No Action, Idle
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Table 123. Command Byte Bit Coding
Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Command Executed Chip Erase Write Fuse Bits Write Lock Bits Write Flash Write EEPROM Read Signature Bytes and Calibration byte Read Fuse and Lock Bits Read Flash Read EEPROM
Table 124. No. of Words in a Page and no. of Pages in the Flash
Flash Size 32K words (64K bytes) Page Size 128 words PCWORD PC[6:0] No. of Pages 256 PCPAGE PC[14:7] PCMSB 14
Table 125. No. of Words in a Page and no. of Pages in the EEPROM
EEPROM Size 2K bytes Page Size 8 bytes PCWORD EEA[2:0] No. of Pages 256 PCPAGE EEA[10:3] EEAMSB 10
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Parallel Programming
Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100 s. 2. Set RESET to "0" and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 121 on page 296 to "0000" and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering Programming mode. Note, if External Crystal or External RC configuration is selected, it may not be possible to apply qualified XTAL1 pulses. In such cases, the following algorithm should be followed: 1. Set Prog_enable pins listed in Table on page 296 to "0000". 2. Apply 4.5 - 5.5V between VCC and GND simultaneously as 11.5 - 12.5V is applied to RESET. 3. Wait 100 s. 4. Re-program the fuses to ensure that External Clock is selected as clock source (CKSEL3:0 = 0b0000) If Lock bits are programmed, a Chip Erase command must be executed before changing the fuses. 5. Exit Programming mode by power the device down or by bringing RESET pin to 0b0. 6. Entering Programming mode with the original algorithm, as described above. Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. * * * The command needs only be loaded once when writing or reading multiple memory locations. Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading.
Chip Erase
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or the EEPROM reprogrammed.
Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is programmed.
Load Command "Chip Erase" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "1000 0000". This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command.
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Programming the Flash The Flash is organized in pages, see Table 123 on page 297. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command "Write Flash" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "0001 0000". This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "0". This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to "1". This selects high data byte. 2. Set XA1, XA0 to "01". This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to "1". This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 140 for signal waveforms). F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the Flash. This is illustrated in Figure 139 on page 300. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "1". This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Program Page 1. Set BS1 = "0". 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low.
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3. Wait until RDY/BSY goes high. (See Figure 140 for signal waveforms.) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to "10". This enables command loading. 2. Set DATA to "0000 0000". This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 139. Addressing the Flash which is Organized in Pages(1)
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE and PCWORD are listed in Table 123 on page 297.
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Figure 140. Programming the Flash Waveforms(1)
F
A
DATA
$10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1. "XX" is don't care. The letters refer to the programming description above.
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Programming the EEPROM
The EEPROM is organized in pages, see Table 124 on page 297. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to "Programming the Flash" on page 299 for details on Command, Address and Data loading): 1. A: Load Command "0001 0001". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF). 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to "0". 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page. (See Figure 141 for signal waveforms.) Figure 141. Programming the EEPROM Waveforms
K
A
DATA
0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" on page 299 for details on Command and Address loading): 1. A: Load Command "0000 0010". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. 5. Set BS to "1". The Flash word high byte can now be read at DATA. 6. Set OE to "1".
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Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" on page 299 for details on Command and Address loading): 1. A: Load Command "0000 0011". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. 5. Set OE to "1". Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to "Programming the Flash" on page 299 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS1 to "0" and BS2 to "0". 4. Give WR a negative pulse and wait for RDY/BSY to go high. Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to "Programming the Flash" on page 299 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS1 to "1" and BS2 to "0". This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to "0". This selects low data byte. Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to "Programming the Flash" on page 299 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS2 to "1" and BS1 to "0". This selects extended data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2 to "0". This selects low data byte.
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Figure 142. Programming the FUSES Waveforms
Write Fuse Low byte A
DATA
0x40
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
0x40
C
DATA XX
C
DATA XX
0x40
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 299 for details on Command and Data loading): 1. A: Load Command "0010 0000". 2. C: Load Data Low Byte. Bit n = "0" programs the Lock bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase.
Reading the Fuse and Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 299 for details on Command loading): 1. A: Load Command "0000 0100". 2. Set OE to "0", BS2 to "0" and BS1 to "0". The status of the Fuse Low bits can now be read at DATA ("0" means programmed). 3. Set OE to "0", BS2 to "1" and BS1 to "1". The status of the Fuse High bits can now be read at DATA ("0" means programmed). 4. Set OE to "0", BS2 to "1" and BS1 to "0". The status of the Extended Fuse bits can now be read at DATA ("0" means programmed). 5. Set OE to "0", BS2 to "0" and BS1 to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). 6. Set OE to "1".
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Figure 143. Mapping Between BS1, BS2 and the Fuse and Lock Bits during Read
Fuse Low Byte
0
Extended Fuse Byte BS2
1
0
DATA
Lock Bits
0 BS1
1
Fuse High Byte BS2
Reading the Signature Bytes
1
The algorithm for reading the Signature bytes is as follows (refer to "Programming the Flash" for details on Command and Address loading): 1. A: Load Command "0000 1000". 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to "0", and BS1 to "0". The selected Signature byte can now be read at DATA. 4. Set OE to "1".
Reading the Calibration Byte
The algorithm for reading the Calibration bytes is as follows (refer to "Programming the Flash" for details on Command and Address loading): 1. A: Load Command "0000 1000". 2. B: Load Address Low Byte, (0x00 - 0x03). 3. Set OE to "0", and BS1 to "1". The Calibration byte can now be read at DATA. 4. Set OE to "1".
Parallel Programming Characteristics
Figure 144. Parallel Programming Timing, Including some General Timing Requirements
t XLWL XTAL1 t DVXH Data & Contol (DATA, XA0/1, BS1, BS2) t BVPH PAGEL WR RDY/BSY t WLRH t PHPL t WL t PLWL
WLRL WH
t XHXL t XLDX
t PLBX
t BVWL
t WLBX
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Figure 145. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA LOAD DATA (HIGH BYTE)
t XLPH t PLXH
LOAD ADDRESS (LOW BYTE)
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 144 (i.e. tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Figure 146. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Timing Requirements(1)
LOAD ADDRESS (LOW BYTE)
t XLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
t BHDV
BS1
t OLDV
OE
t OHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 144 (i.e. tDVXH, tXHXL, and tXLDX) also apply to reading operation.
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Table 126. Parallel Programming Characteristics, VCC = 5V 10%
Symbol VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH tPLXH tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: 1. Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before XTAL1 High XTAL1 Low to XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low XTAL1 Low to PAGEL high PAGEL low to XTAL1 high BS1 Valid before PAGEL High PAGEL Pulse Width High BS1 Hold after PAGEL Low BS2/1 Hold after WR Low PAGEL Low to WR Low BS1 Valid to WR Low WR Pulse Width Low WR Low to RDY/BSY Low WR Low to RDY/BSY High(1) WR Low to RDY/BSY High for Chip Erase(2) XTAL1 Low to OE Low BS1 Valid to DATA valid OE Low to DATA Valid OE High to DATA Tri-stated 67 200 150 67 0 0 150 67 150 67 67 67 67 150 0 3.7 7.5 0 0 250 250 250 1 4.5 9 Min 11.5 Typ Max 12.5 250 Units V A ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ms ns ns ns ns
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 127 on page 308, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO are used to describe the serial data in and serial data out, respectively. For ATmega64, these pins are mapped to PDI and PDO.
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SPI Serial Programming Pin Mapping
Even though the SPI Programming interface re-uses the SPI I/O module, there is one important difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Programming mode as shown in Table 127. Table 127. Pin Mapping SPI Serial Programming
Symbol MOSI (PDI) MISO (PDO) SCK Pins PE0 PE1 PB1 I/O I O I Description Serial Data In Serial Data Out Serial Clock
Figure 147. SPI Serial Programming and Verify(1)
+2.7 - 5.5V VCC
MOSI MISO SCK
PE0 PE1 PB1 XTAL1 AVCC
+2.7 - 5.5V (2)
RESET
GND
Notes:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck 12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck 12 MHz SPI Serial Programming Algorithm When writing serial data to the ATmega64, data is clocked on the rising edge of SCK. When reading data from the ATmega64, data is clocked on the falling edge of SCK. See Figure 148 for timing details. To program and verify the ATmega64 in the SPI Serial Programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer cannot guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two
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CPU clock cycles duration after SCK has been set to "0". As an alternative to using the RESET signal, PEN can be held low during Poweron Reset while SCK is set to "0". In this case, only the PEN value at Power-on Reset is important. If the programmer cannot guarantee that SCK is held low during Power-up, the PEN method cannot be used. The device must be powered down in order to commence normal operation when using this method. 2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming Enable serial instruction to pin MOSI. 3. The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The Page size is found in Table 124 on page 297. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 128). Accessing the SPI Serial Programming interface before the Flash write operation completes can result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 128). 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off.
Note: If other commands that polling (read) are applied before any write operation (FLASH, EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming.
Data Polling Flash
When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip -erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 128 for tWD_FLASH value.
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Data Polling EEPROM
When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-programmed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least t WD_EEPROM before programming the next byte. See Table 128 for tWD_EEPROM value. Table 128. Minimum Wait Delay before Writing the Next Flash or EEPROM Location
Symbol tWD_FUSE tWD_FLASH(1) tWD_EEPROM tWD_ERASE Note: 1. Flash write: per page Minimum Wait Delay 4.5 ms 4.5 ms 9.0 ms 9.0 ms
Figure 148. SPI Serial Programming Waveforms
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
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Table 129. SPI Serial Programming Instruction Set
Instruction Format Instruction Programming Enable Chip Erase Read Program Memory Byte 1 1010 1100 1010 1100 0010 H000 Byte 2 0101 0011 100x xxxx xaaa aaaa Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb Byte4 xxxx xxxx xxxx xxxx oooo oooo Operation Enable SPI Serial Programming after RESET goes low. Chip Erase EEPROM and Flash. Read H (high or low) data o from Program memory at word address a:b. Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before data high byte is applied within the same address. Write Program Memory Page at address a:b. Read data o from EEPROM memory at address a:b. Write data i to EEPROM memory at address a:b. Read Lock bits. "0" = programmed, "1" = unprogrammed. See Table 115 on page 291 for details. Write Lock bits. Set bits = "0" to program Lock bits. See Table 115 on page 291 for details. Read Signature Byte o at address b. Set bits = "0" to program, "1" to unprogram. See Table 119 on page 293 for details. Set bits = "0" to program, "1" to unprogram. See Table 118 on page 293 for details. Set bits = "0" to program, "1" to unprogram. See Table 119 on page 293 for details. Read Fuse bits. "0" = programmed, "1" = unprogrammed. See Table 119 on page 293 for details.
Load Program Memory Page
0100 H000
xxxx xxxx
xbbb bbbb
iiii iiii
Write Program Memory Page Read EEPROM Memory Write EEPROM Memory Read Lock Bits
0100 1100 1010 0000 1100 0000 0101 1000
xaaa aaaa xxxx xaaa xxxx xaaa 0000 0000
bxxx xxxx bbbb bbbb bbbb bbbb xxxx xxxx
xxxx xxxx oooo oooo iiii iiii xxoo oooo
Write Lock Bits
1010 1100
111x xxxx
xxxx xxxx
11ii iiii
Read Signature Byte Write Fuse Bits
0011 0000 1010 1100
xxxx xxxx 1010 0000
xxxx xxbb xxxx xxxx
oooo oooo iiii iiii
Write Fuse High Bits
1010 1100
1010 1000
xxxx xxxx
iiii iiii
Write Extended Fuse Bits
1010 1100
1010 0100
xxxx xxxx
xxxx xxii
Read Fuse Bits
0101 0000
0000 0000
xxxx xxxx
oooo oooo
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Table 129. SPI Serial Programming Instruction Set (Continued)
Instruction Format Instruction Read Extendend Fuse Bits Byte 1 0101 0000 Byte 2 0000 1000 Byte 3 xxxx xxxx Byte4 oooo oooo Operation Read Extended Fuse bits. "0" = pro-grammed, "1" = unprogrammed. See Table 119 on page 293 for details. Read Fuse high bits. "0" = programmed, "1" = unprogrammed. See Table 118 on page 293 for details. Read Calibration Byte o at address b.
Read Fuse High Bits
0101 1000
0000 1000
xxxx xxxx
oooo oooo
Read Calibration Byte Note:
0011 1000
00xx xxxx
0000 00bb
oooo oooo
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care
SPI Serial Programming Characteristics
For characteristics of the SPI module, see "SPI Timing Characteristics" on page 332.
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Programming Via the JTAG Interface
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or Onchip Debug. In these cases the JTAG pins must be dedicated for this purpose. As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers. Programming Specific JTAG Instructions The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for Programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 149.
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Figure 149. State Machine Sequence for Changing the Instruction Word
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
AVR_RESET (0xC)
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched. The active states are: * Shift-DR: The Reset Register is shifted by the TCK input.
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PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming Enable Register is selected as data register. The active states are the following: * * Shift-DR: the Programming enable signature is shifted into the data register. Update-DR: The programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid.
PROG_COMMANDS (0x5)
The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as data register. The active states are the following: * * * * Capture-DR: The result of the previous command is loaded into the data register. Shift-DR: The data register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command. Update-DR: The programming command is applied to the Flash inputs Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see Table 130 on page 318).
PROG_PAGELOAD (0x6)
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. The 1024-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the Shift Register. The data are automatically transferred to the Flash page buffer byte-by-byte in the Shift-DR state by an internal state machine. This is the only active state: * Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically loaded into the Flash page one byte at a time.
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used.
Note:
PROG_PAGEREAD (0x7)
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port. The 1032-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to the Shift Register. The data are automatically transferred from the Flash page buffer byte-by-byte in the Shift-DR state by an internal state machine. This is the only active state: * Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the TCK input. The TDI input is ignored.
The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used.
Note:
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Data Registers
The data registers are selected by the JTAG instruction registers described in section "Programming Specific JTAG Instructions" on page 313. The data registers relevant for programming operations are: * * * * * Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register
Reset Register
The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering programming mode. A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out Period (refer to "Clock Sources" on page 38) after releasing the Reset Register. The output from this data register is not latched, so the reset will take place immediately, as shown in Figure 126 on page 257.
Programming Enable Register
The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 150. Programming Enable Register
TDI
D A T A
$A370
=
D
Q
Programming Enable
ClockDR & PROG_ENABLE
TDO
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Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 130. The state sequence when shifting in the programming commands is illustrated in Figure 152. Figure 151. Programming Command Register
TDI
S T R O B E S A D D R E S S / D A T A
Flash EEPROM Fuses Lock Bits
TDO
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Table 130. JTAG Programming Instruction Set
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care Instruction 1a. Chip Erase TDI sequence 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 0110011_10000000 0100011_00010000 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0010111_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0100011_00000010 0000111_aaaaaaaa 0000011_bbbbbbbb 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00010001 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000011 0000111_aaaaaaaa 0000011_bbbbbbbb TDO sequence xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (9) (1) (9) low byte high byte (9) (1) (9) (2) Notes
1b. Poll for Chip Erase Complete 2a. Enter Flash Write 2b. Load Address High Byte 2c. Load Address Low Byte 2d. Load Data Low Byte 2e. Load Data High Byte 2f. Latch Data
2g. Write Flash Page
(1)
2h. Poll for Page Write Complete 3a. Enter Flash Read 3b. Load Address High Byte 3c. Load Address Low Byte 3d. Read Data Low and High Byte
(2)
4a. Enter EEPROM Write 4b. Load Address High Byte 4c. Load Address Low Byte 4d. Load Data Byte 4e. Latch Data
4f. Write EEPROM Page
(1)
4g. Poll for Page Write Complete 5a. Enter EEPROM Read 5b. Load Address High Byte 5c. Load Address Low Byte
(2)
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Table 130. JTAG Programming Instruction Set (Continued)
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care Instruction 5d. Read Data Byte TDI sequence 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 0100011_01000000
(6)
TDO sequence xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo
Notes
6a. Enter Fuse Write 6b. Load Data Low Byte
0010011_iiiiiiii 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 0111011_00000000 0010011_iiiiiiii 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0010011_iiiiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00100000 0010011_11iiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000100
(6)
(3) (1)
6c. Write Fuse Extended Byte
6d. Poll for Fuse Write Complete 6e. Load Data Low Byte
(7)
(2) (3) (1)
6f. Write Fuse High Byte
6g. Poll for Fuse Write Complete 6h. Load Data Low Byte 6i. Write Fuse Low byte
(8)
(2) (3) (1)
6j. Poll for Fuse Write Complete 7a. Enter Lock Bit Write 7b. Load Data Byte(9) 7c. Write Lock Bits
(2)
(4) (1)
7d. Poll for Lock Bit Write Complete 8a. Enter Fuse/Lock Bit Read 8b. Read Fuse Extended Byte 8c. Read Fuse High Byte(7) 8d. Read Fuse Low Byte(8) 8e. Read Lock Bits(9)
(2)
0111010_00000000 0111111_00000000 0111110_00000000 0111111_00000000 0110010_00000000 0110011_00000000 0110110_00000000 0110111_00000000
(5)
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Table 130. JTAG Programming Instruction Set (Continued)
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care Instruction 8f. Read Fuses and Lock Bits TDI sequence 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00001000 0000011_bbbbbbbb 0110010_00000000 0110011_00000000 0100011_00001000 0000011_bbbbbbbb 0110110_00000000 0110111_00000000 TDO sequence xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo Notes (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits
9a. Enter Signature Byte Read 9b. Load Address Byte 9c. Read Signature Byte 10a. Enter Calibration Byte Read 10b. Load Address Byte 10c. Read Calibration Byte Notes:
1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = "1". 3. Set bits to "0" to program the corresponding fuse, "1" to unprogram the fuse. 4. Set bits to "0" to program the corresponding Lock bit, "1" to leave the Lock bit unchanged. 5. "0" = programmed, "1" = unprogrammed. 6. The bit mapping for Fuses Extended byte is listed in Table 117 on page 292. 7. The bit mapping for Fuses High byte is listed in Table 118 on page 293. 8. The bit mapping for Fuses Low byte is listed in Table 119 on page 293. 9. The bit mapping for Lock bits byte is listed in Table 115 on page 291. 10. Address bits exceeding PCMSB and EEAMSB (Table 123 and Table 124) are don't care.
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Figure 152. State Machine Sequence for Changing/Reading the Data Word
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
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Virtual Flash Page Load Register
The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically transferred to the Flash page buffer byte-by-byte. Shift in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to load the entire Flash page buffer before executing Page Write. Figure 153. Virtual Flash Page Load Register
STROBES
State Machine
ADDRESS
TDI
Flash EEPROM Fuses Lock Bits
D A T A
TDO
Virtual Flash Page Read Register
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte-by-byte. The first eight cycles are used to transfer the first byte to the internal Shift Register, and the bits that are shifted out during these eight cycles should be ignored. Following this initialization, data are shifted out starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to read one full Flash page to verify programming.
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Figure 154. Virtual Flash Page Read Register
STROBES
State Machine
ADDRESS
TDI
Flash EEPROM Fuses Lock Bits
D A T A
TDO
Programming Algorithm Entering Programming Mode
All references below of type "1a", "1b", and so on, refer to Table 130. 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register.
Leaving Programming Mode
1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the Programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.
Performing Chip Erase
1. Enter JTAG instruction PROG_COMMANDS. 2. Start chip erase using programming instruction 1a. 3. Poll for chip erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 1 on page 306).
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Programming the Flash
Before programming the Flash, a Chip Erase must be performed. See "Performing Chip Erase" on page 323. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address high byte using programming instruction 2b. 4. Load address low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 1 on page 306). 9. Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 123 on page 297) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 1 on page 306). 9. Repeat steps 3 to 8 until all data have been programmed.
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Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 123 on page 297) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first eight bits shifted out should be ignored. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. Programming the EEPROM Before programming the EEPROM, a Chip Erase must be performed. See "Performing Chip Erase" on page 323. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address high byte using programming instruction 4b. 4. Load address low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 1 on page 306). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM. Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM
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Programming the Fuses
1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data Low byte using programming instructions 6b. A bit value of "0" will program the corresponding fuse, a "1" will unprogram the fuse. 4. Write Fuse Extended byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 1 on page 306). 6. Load data Low byte using programming instructions 6e. A bit value of "0" will program the corresponding fuse, a "1" will unprogram the fuse. 7. Write Fuse High byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 1 on page 306). 9. Load data low byte using programming instructions 6h. A "0" will program the fuse, a "1" will unprogram the fuse. 10. Write Fuse low byte using programming instruction 6i. 11. Poll for Fuse write complete using programming instruction 6j, or wait for tWLRH (refer to Table 1 on page 306).
Programming the Lock Bits
1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of "0" will program the corresponding Lock bit, a "1" will leave the Lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 1 on page 306).
Reading the Fuses and Lock Bits
1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8f. To only read Fuse Extended byte, use programming instruction 8b. To only read Fuse High byte, use programming instruction 8c. To only read Fuse Low byte, use programming instruction 8d. To only read Lock bits, use programming instruction 8e.
Reading the Signature Bytes
1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively.
Reading the Calibration Byte
1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c.
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Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins..................... 200.0 - 400.0mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol VIL VIH VIL1 VIH1 VIL2 VIH2 VOL VOH IIL IIH RRST RPEN RPU Parameter Input Low Voltage except XTAL1 and RESET pins Input High Voltage except XTAL1 and RESET pins Input Low Voltage XTAL1 pin Input High Voltage XTAL1 pin Input Low Voltage RESET pin Input High Voltage RESET pin Output Low Voltage(3) (Ports A,B,C,D, E, F, G) Output High Voltage(4) (Ports A,B,C,D, E, F, G)) Input Leakage Current I/O Pin Input Leakage Current I/O Pin Reset Pull-up Resistor PEN Pull-up Resistor I/O Pin Pull-up Resistor Condition VCC=2.7V - 5.5V VCC=2.7V - 5.5V VCC=2.7V - 5.5V VCC=2.7V - 5.5V VCC=2.7V - 5.5V VCC=2.7V - 5.5V IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V Vcc = 5.5V, pin low (absolute value) Vcc = 5.5V, pin high (absolute value) 30 30 20 4.2 2.2 1.0 1.0 60 60 50 Min -0.5 0.6 VCC(2) -0.5 0.7 VCC(2) -0.5 0.85 VCC(2) Typ Max 0.2 VCC(1) VCC + 0.5 0.1 VCC(1) VCC + 0.5 0.2 VCC(1) VCC + 0.5 0.7 0.5 Units V V V V V V V V V V A A k k k
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DC Characteristics
TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Active 4 MHz, VCC = 3V (ATmega64L) Active 8 MHz, VCC = 5V (ATmega64) Power Supply Current ICC Idle 4 MHz, VCC = 3V (ATmega64L) Idle 8 MHz, VCC = 5V (ATmega64) Power-down mode(5) Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current Analog Comparator Propagation Delay WDT enabled, VCC = 3V WDT disabled, VCC = 3V VACIO IACLK tACPD Notes: VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -40 -50 750 500 < 10 <4 2 12 20 10 40 50 mA mA A A mV nA ns Min Typ Max 5 20 Units mA mA
1. "Max" means the highest value where the pin is guaranteed to be read as low 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V.
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External Clock Drive Waveforms
Figure 155. External Clock Drive Waveforms
V IH1 V IL1
External Clock Drive
Table 131. External Clock Drive(1)
VCC = 2.7V to 5.5V Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Change in period from one clock cycle to the next Min 0 125 50 50 1.6 1.6 2 Max 8 VCC = 4.5V to 5.5V Min 0 62.5 25 25 0.5 0.5 2 Max 16 Units MHz ns ns ns s s %
tCLCL
Note:
1. Refer to "External Clock" on page 44 for details.
Table 132. External RC Oscillator, Typical Frequencies
R [k](1) 31.5 6.5 Notes: C [pF] 20 20 f(2) 650 kHz 2.0 MHz
1. R should be in the range 3k - 100k, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout.
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Two-wire Serial Interface Characteristics
Table 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega64 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 156. Table 133. Two-wire Serial Bus Requirements
Symbol VIL VIH Vhys tr(1) tof(1) tSP(1) Ii Ci(1) fSCL
(1)
Parameter Input Low-voltage Input High-voltage Hysteresis of Schmitt Trigger Inputs Output Low-voltage Rise Time for both SDA and SCL Output Fall Time from VIHmin to VILmax Spikes Suppressed by Input Filter Input Current each I/O Pin Capacitance for each I/O Pin SCL Clock Frequency
Condition
Min -0.5 0.7 VCC 0.05 VCC
(2)
Max 0.3 VCC VCC + 0.5 - 0.4
(3)(2)
Units V V V V ns ns ns A pF kHz s s s s s s s s s s ns ns s s s
VOL(1)
3 mA sink current
0 20 + 0.1Cb
300 250 50
(2)
10 pF < Cb < 400 pF(3)
20 + 0.1Cb(3)(2) 0
0.1VCC < Vi < 0.9VCC fCK(4) > max(16fSCL, 250 kHz)(5) fSCL 100 kHz
-10 - 0 V CC - 0,4V ---------------------------3mA V CC - 0,4V ---------------------------3mA 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7
10 10 400 1000ns -----------------Cb 300ns --------------Cb - - - - - - - - 3.45 0.9 - - - - -
Rp
Value of Pull-up resistor fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz Low Period of the SCL Clock fSCL 100 kHz
(6)
tHD;STA
Hold Time (repeated) START Condition
tLOW
fSCL > 100 kHz(7) fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz
tHIGH
High period of the SCL clock
tSU;STA
Set-up time for a repeated START condition
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO tBUF Notes: 1. 2. 3. 4.
Setup time for STOP condition Bus free time between a STOP and START condition
fSCL 100 kHz
In ATmega64, this parameter is characterized and not 100% tested. Required only for fSCL > 100 kHz. Cb = capacitance of one bus line in pF. fCK = CPU clock frequency
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5. This requirement applies to all ATmega64 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega64 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz. 7. The actual low period generated by the ATmega64 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega64 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega64 devices, as well as any other device with a proper tLOW acceptance margin.
Figure 156. Two-wire Serial Bus Timing
tof tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tHIGH tLOW tr
tBUF
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SPI Timing Characteristics
See Figure 157 on page 332 and Figure 158 on page 333 for details. Table 134. SPI Timing Parameters
Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note: SCK period SCK high/low Rise/Fall time Setup Hold Out to SCK SCK to out SCK to out high SS low to out SCK period SCK high/low
(1)
Mode Master Master Master Master Master Master Master Master Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave
Min
Typ See Table 72 50% duty cycle 3.6 10 10 0.5 * tsck 10 10 15
Max
ns
4 * tck 2 * tck 1.6 10 tck 15 20 10 20 ns s
Rise/Fall time Setup Hold SCK to out SCK to SS high SS high to tri-state SS low to SCK
1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK >12 MHz
Figure 157. SPI Interface Timing Requirements (Master Mode)
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
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Figure 158. SPI Interface Timing Requirements (Slave Mode)
18
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
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ADC Characteristics
Table 135. ADC Characteristics, Single Ended Channels, -40C - 85C
Symbol Parameter Resolution Condition Single Ended Conversion Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz Absolute Accuracy (Including INL, DNL, Quantization Error, Gain and Offset Error) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Noise Reduction mode Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz Noise Reduction mode Integral Non-Linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz 50 13 VCC -0.3 2.0 GND 0 38.5 2.4 2.56 32 100 2.8
(1)
Min
Typ
Max 10
Units Bits LSB
1.5
3
LSB
1.5
LSB
3
LSB
0.75
LSB
Differential Non-Linearity (DNL)
0.25
LSB
Gain Error
0.75
LSB
Offset error Clock Frequency Conversion Time AVCC VREF VIN Analog Supply Voltage Reference Voltage Input Voltage ADC Conversion Output Input Bandwidth VINT RREF RAIN Notes: Internal Voltage Reference Reference Input Resistance Analog Input Resistance 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V.
0.75 1000 260 VCC + 0.3 AVCC VREF 1023
(2)
LSB kHz s V V V LSB kHz V k M
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Table 136. ADC Characteristics, Differential Channels, -40C - 85C
Symbol Parameter Condition Gain = Resolution 1x Min Typ Max 10 10 10 16 Units Bits Bits Bits LSB
Gain = 10x Gain = 200x Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz
Absolute Accuracy
Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz
16
LSB
8
LSB
0.75
LSB
Integral Non-Linearity (INL) (Accuracy after Calibration for Offset and Gain Error)
Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 1x
0.75
LSB
2.5 1.6 1.6 0.3 1.5
LSB % % % LSB
Gain Error
Gain = 10x Gain = 200x Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz
Offset Error
Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz
1
LSB
6 50 13 VCC -0.3(1) 2.0 GND -VREF/Gain -511 4 1000 260 VCC + 0.3
(2)
LSB kHz s V V V V LSB kHz
Clock Frequency Conversion Time AVCC VREF VIN VDIFF Analog Supply Voltage Reference Voltage Input Voltage Input Differential Voltage ADC Conversion Output Input Bandwidth
AVCC - 0.5 VCC VREF/Gain 511
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Table 136. ADC Characteristics, Differential Channels, -40C - 85C (Continued)
Symbol VINT RREF RAIN Notes: Parameter Internal Voltage Reference Reference Input Resistance Analog Input Resistance 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. Condition Min 2.3 Typ 2.56 32 100 Max 2.7 Units V k M
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External Data Memory Timing
Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
8 MHz Oscillator Symbol 0 1 2 3a 3b 4 5 6 7 8 9 10 11 12 13 14 15 16 Notes: 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX tRLRH tDVWL tWHDX tDVWH tWLWH Parameter Oscillator Frequency ALE Pulse Width Address Valid A to ALE Low Address Hold After ALE Low, write access Address Hold after ALE Low, read access Address Valid C to ALE Low Address Valid to RD Low Address Valid to WR Low ALE Low to WR Low ALE Low to RD Low Data Setup to RD High Read Low to Data Valid Data Hold After RD High RD Pulse Width Data Setup to WR Low Data Hold After WR High Data Valid to WR High WR Pulse Width 0 115 42.5 115 125 115 115 57.5 5 5 57.5 115 115 47.5 47.5 40 75 0 1.0tCLCL-10 0.5tCLCL-20
(1)
Variable Oscillator Min 0.0 1.0tCLCL-10 0.5tCLCL-5(1) 5 5 0.5tCLCL-5
(1)
Min
Max
Max 16
Unit MHz ns ns ns ns ns ns ns
1.0tCLCL-10 1.0tCLCL-10 67.5 67.5 0.5tCLCL-15(2) 0.5tCLCL-15 40 1.0tCLCL-50
(2)
0.5tCLCL+5(2) 0.5tCLCL+5
(2)
ns ns ns ns ns ns ns ns ns ns
1.0tCLCL-10 1.0tCLCL 1.0tCLCL-10
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 138. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state
8 MHz Oscillator Symbol 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 240 240 240 200 2.0tCLCL-10 2.0tCLCL 2.0tCLCL-10 Min Max Variable Oscillator Min 0.0 Max 16 2.0tCLCL-50 Unit MHz ns ns ns ns
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Table 139. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4 MHz Oscillator Symbol 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 365 375 365 325 3.0tCLCL-10 3.0tCLCL 3.0tCLCL-10 Min Max Variable Oscillator Min 0.0 Max 16 3.0tCLCL-50 Unit MHz ns ns ns ns
Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4 MHz Oscillator Symbol 0 10 12 14 15 16 1/tCLCL tRLDV tRLRH tWHDX tDVWH tWLWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Hold After WR High Data Valid to WR High WR Pulse Width 365 240 375 365 325 3.0tCLCL-10 2.0tCLCL-10 3.0tCLCL 3.0tCLCL-10 Min Max Variable Oscillator Min 0.0 Max 16 3.0tCLCL-50 Unit MHz ns ns ns ns ns
Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state
4 MHz Oscillator Symbol 0 1 2 3a 3b 4 5 6 7 8 9 10 11 12 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX tRLRH Parameter Oscillator Frequency ALE Pulse Width Address Valid A to ALE Low Address Hold After ALE Low, write access Address Hold after ALE Low, read access Address Valid C to ALE Low Address Valid to RD Low Address Valid to WR Low ALE Low to WR Low ALE Low to RD Low Data Setup to RD High Read Low to Data Valid Data Hold After RD High RD Pulse Width 0 235 235 115 5 5 115 235 235 115 115 45 190 0 1.0tCLCL-15 130 130 Min Max Variable Oscillator Min 0.0 tCLCL-15 0.5tCLCL-10 5 5 0.5tCLCL-10(1) 1.0tCLCL-15 1.0tCLCL-15 0.5tCLCL-10
(2) (2) (1)
Max 8
Unit MHz ns ns ns ns ns ns ns
0.5tCLCL+5
ns ns ns
0.5tCLCL-10(2) 45
0.5tCLCL+5(2)
1.0tCLCL-60
ns ns ns
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Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)
4 MHz Oscillator Symbol 13 14 15 16 Notes: tDVWL tWHDX tDVWH tWLWH Parameter Data Setup to WR Low Data Hold After WR High Data Valid to WR High WR Pulse Width Min 105 235 250 235 Max Variable Oscillator Min 0.5tCLCL-20
(1)
Max
Unit ns ns ns ns
1.0tCLCL-15 1.0tCLCL 1.0tCLCL-15
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
4 MHz Oscillator Symbol 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 485 500 485 440 2.0tCLCL-15 2.0tCLCL 2.0tCLCL-15 Min Max Variable Oscillator Min 0.0 Max 8 2.0tCLCL-60 Unit MHz ns ns ns ns
Table 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4 MHz Oscillator Symbol 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 735 750 735 690 3.0tCLCL-15 3.0tCLCL 3.0tCLCL-15 Min Max Variable Oscillator Min 0.0 Max 8 3.0tCLCL-60 Unit MHz ns ns ns ns
Table 144. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4 MHz Oscillator Symbol 0 10 12 14 15 16 1/tCLCL tRLDV tRLRH tWHDX tDVWH tWLWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Hold After WR High Data Valid to WR High WR Pulse Width 735 485 750 735 690 3.0tCLCL-15 2.0tCLCL-15 3.0tCLCL 3.0tCLCL-15 Min Max Variable Oscillator Min 0.0 Max 8 3.0tCLCL-60 Unit MHz ns ns ns ns ns
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Figure 159. External Memory Timing (SRWn1 = 0, SRWn0 = 0
T1 T2 T3 T4
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
A15:8
Prev. addr.
6
16
14
WR
3b 9 Data 10 8 12 11
DA7:0 (XMBK = 0)
Address 5
RD
Figure 160. External Memory Timing (SRWn1 = 0, SRWn0 = 1)
T1 T2 T3 T4 T5
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
A15:8
Prev. addr.
6
16
14
WR
3b 9 Data 10 8 12 11
DA7:0 (XMBK = 0)
Address 5
RD
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Read
Write
DA7:0
Prev. data
Address
Data
Read
Write
DA7:0
Prev. data
Address
Data
ATmega64(L)
Figure 161. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
T1 T2 T3 T4 T5 T6
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
A15:8
Prev. addr.
6
16
14
WR
3b 9 Data 10 8 12 11
DA7:0 (XMBK = 0)
Address 5
RD
Figure 162. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)
T1 T2 T3 T4 T5 T6 T7
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
Write
A15:8
Prev. addr.
DA7:0
Prev. data
Address 6
Data 16 14
WR
3b 9 Data 10 8 12
Read
11
DA7:0 (XMBK = 0)
Address 5
RD
Note:
1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).
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Read
Write
DA7:0
Prev. data
Address
Data
Typical Characteristics
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: Operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
Active Supply Current
Figure 163. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 2.5 5.5 V 5.0 V 2 4.5 V 1.5 4.0 V 3.6 V 3.3 V 1 2.7 V
Icc(m A)
0.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz)
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Figure 164. Active Supply Current vs. Frequency (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
45 40 35 30
Icc (mA)
5.5 V 5.0 V
25 4.5 V 20 15 10 5 0 0 2 4 6 8 10 12 14 16 18 20
4.0 V 3.6 V 3.0 V
Frequency (MHz)
Figure 165. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 1 MHz 2.8 2.6 2.4 2.2
Icc (mA)
85 C -40 C
2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
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Figure 166. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 2 MHz 5.5 5 4.5
Icc (mA)
85 C 25 C -40 C
4 3.5 3 2.5 2 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Figure 167. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 4 MHz 11 10 9 8 7 6 5 4 3 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5 25 C -40 C 85 C
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Icc (mA)
ATmega64(L)
Figure 168. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 8 MHz 20 18 16
Icc (mA)
-40 C 25 C 85 C
14 12 10 8 6 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Figure 169. Active Supply Current vs. VCC (32 kHz External Oscillator)
ACTIVE SUPPLY CURRENT vs. Vcc
32kHz EXTERNAL OSCILLATOR 130 120 110 100
Icc (uA)
25 C
90 80 70 60 50 40 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
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Idle Supply Current
Figure 170. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 5.5 V 5.0 V 4.5 V
Icc (mA)
4.0 V 3.6 V 3.3 V 2.7 V
Figure 171. Idle Supply Current vs. Frequency (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 25 5.5V 20 5.0V
4.5V
Icc (mA)
15
10 4.0V 5
0 0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
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Figure 172. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 1 MHz 1.6 85 C 25 C -40 C
1.4
1.2
Icc (mA)
1
0.8
0.6
0.4 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Figure 173. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 2 MHz 3 85 C 25 C -40 C 2.5
Icc (mA)
2
1.5
1
0.5 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
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Figure 174. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 4 MHz 6 5.5 5 4.5
Icc (mA)
25 C 85 C -40 C
4 3.5 3 2.5 2 1.5 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Figure 175. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR. 8 MHz 11 10 9 8
Icc (mA)
-40 C 25 C 85 C
7 6 5 4 3 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
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2490L-AVR-10/06
ATmega64(L)
Figure 176. Idle Supply Current vs. VCC (32 kHz External Oscillator)
IDLE SUPPLY CURRENT vs. Vcc
32kHz EXTERNAL OSCILLATOR 80 75 70 65 60
Icc (uA)
25 C
55 50 45 40 35 30 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Power-Down Supply Current
Figure 177. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED 4 3.5 3 2.5
Icc (uA )
85 C
2 1.5 1 0.5 0 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5 -40 C 25 C
349
2490L-AVR-10/06
Figure 178. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER ENABLED 25
20
85 C 25 C -40 C
15
Icc (uA)
10
5
0 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Power-Save Supply Current
Figure 179. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-SAVE SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED 14 25 C 12 10 8 6 4 2 0 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
350
ATmega64(L)
2490L-AVR-10/06
Icc (uA)
ATmega64(L)
Standby Supply Current Figure 180. Standby Supply Current vs. VCC
STANDBY SUPPLY CURRENT vs. Vcc
0.2 0.18 6MHz Res 0.16 0.14
Icc (mA)
6MHz Xtal
0.12 0.1 0.08 0.06 0.04 0.02 2.5 3 3.5 4 Vcc (V) 4.5 5
4MHz Res 4MHz Xtal
2MHz Xtal 2MHz Res 455KHz Res 1MHz Res
5.5
Figure 181. Standby Supply Current vs. VCC (CKOPT Programmed)
STANDBY SUPPLY CURRENT vs. Vcc
CKOPT programmed 3 16MHz Xtal 2.5 12MHz Xtal 2
Icc (mA)
1.5
6MHz Xtal 4MHz Xtal
1
0.5
0 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
351
2490L-AVR-10/06
Pin Pull-up
Figure 182. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
V cc = 5V 160 140 120 100
IOP (uA)
25 C 85 C -40 C
80 60 40 20 0 0 0.5 1 1.5 2 2.5 V (V) OP 3 3.5 4 4.5 5
Figure 183. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V 80 -40 C 70 60 85 C 50
IOP (uA)
25 C
40 30 20 10 0 0 0.5 1 1.5 VOP(V) 2 2.5 3
352
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Figure 184. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5V 120 -40 C 100 25 C
85 C 80
IRESET (uA)
60
40
20
0 0 0.5 1 1.5 2 2.5 VRESET (V) 3 3.5 4 4.5 5
Figure 185. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7V 60 -40 C 50 85 C 40
IRESET (uA)
25 C
30
20
10
0 0 0.5 1 1.5 VRESET (V) 2 2.5 3
353
2490L-AVR-10/06
Figure 186. PEN Pull-up Resistor Current vs. PEN Pin Voltage (VCC = 5V)
PEN PULL-UP RESISTOR CURRENT vs. PEN PIN VOLTAGE
Vcc = 5V 140 -40 C 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VPEN (V) 3 3.5 4 4.5 5 25 C
85 C
Figure 187. PEN Pull-up Resistor Current vs. PEN Pin Voltage (VCC = 2.7V)
PEN PULL-UP RESISTOR CURRENT vs. PEN PIN VOLTAGE
80 -40 C 70 60 50 40 30 20 10 0 0 0.5 1 1.5 VPEN (V) 2 2.5 3 25 C 85 C VCC = 2.7V
354
ATmega64(L)
2490L-AVR-10/06
IPEN (uA)
IPEN (uA)
ATmega64(L)
Pin Driver Strength Figure 188. I/O Pin Source Current vs. Output Voltage (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 80 -40 C 70 25 C 85 C 60 50
IOH (mA)
40 30 20 10 0 3 3.2 3.4 3.6 3.8 4 VOH (V) 4.2 4.4 4.6 4.8 5
Figure 189. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 30 -40 C 25 C 85 C 20
IOH (mA)
25
15
10
5
0 0.5 1 1.5 VOH (V) 2 2.5 3
355
2490L-AVR-10/06
Figure 190. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 80 70 60 50
IOL (mA)
-40 C 25 C 85 C
40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
Figure 191. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 30 -40 C 25 C 85 C 20
IOL (mA)
25
15
10
5
0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
356
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Pin Thresholds and Hysteresis Figure 192. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1')
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIH. IO PIN READ AS '1' 2.4 2.2 2
Threshold (V)
-40 C 85 C 25 C
1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Figure 193. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0')
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIL. IO PIN READ AS '0' 1.5 1.4 1.3
Threshold (V)
-40 C 25 C 85 C
1.2 1.1 1 0.9 0.8 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
357
2490L-AVR-10/06
Figure 194. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT HYSTERESIS vs. Vcc
0.8
0.6
-40 C 25 C 85 C
Threshold (V)
0.4
0.2
0 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Figure 195. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1')
RESET INPUT THRESHOLD VOLTAGE vs. Vcc
VIH. IO PIN READ AS '1' 2.4 2.2 2
Threshold (V)
1.8 1.6 -40 C 1.4 25 C 1.2 1 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5 85 C
358
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Figure 196. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0')
RESET INPUT THRESHOLD VOLTAGE vs. Vcc
VIL. IO PIN READ AS '0' 2.4 2.2 2
Threshold (V)
85 C 25 C -40 C
1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
Figure 197. Reset Input Pin Hysteresis vs. VCC
RESET INPUT PIN HYSTERESIS vs. Vcc
0.35 -40 C 0.3 0.25
Hysteresis (V)
0.2 25 C 0.15 0.1 0.05 85 C 0 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
359
2490L-AVR-10/06
BOD Thresholds and Analog Comparator Offset
Figure 198. BOD Thresholds vs. Temperature (BODLEVEL is 4.0V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 4.0 V 4
3.95
Rising Vcc
Threshold (V)
3.9
3.85 Falling Vcc 3.8
3.75 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (C)
Figure 199. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 2.7 V 2.8 2.78 2.76 2.74
Thres hold (V)
Rising Vcc
2.72 2.7 2.68 2.66 2.64 2.62 2.6 -40 -20 0 20 Temperature (C) 40 60 80 Falling Vcc
360
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Figure 200. Bandgap Voltage vs. VCC
BANDGAP VOLTAGE vs. VCC
1.275
1.27
85 C -40 C
Bandgap Voltage (V)
1.265
25 C
1.26
1.255
1.25 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Internal Oscillator Speed
Figure 201. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. Vcc
1060 1050 1040 1030 1020
FRC (k Hz)
-40 C 25 C 85 C
1010 1000 990 980 970 960 950 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
361
2490L-AVR-10/06
Figure 202. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
1.02
1
5.5 V 5.0 V
0.98
FRC (MHz )
4.5 V 4.0 V
0.96
3.6 V 3.3 V
0.94
2.7 V
0.92
0.9 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (C)
Figure 203. Calibrated 1 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. Vcc
1.02 -40 C 25 C 1 85 C
0.98
F RC (MHz )
0.96
0.94
0.92
0.9 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
362
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Figure 204. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
1.5 25 C 1.4 1.3 1.2 1.1
F (MHz) RC
1 0.9 0.8 0.7 0.6 0.5 0.4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
Figure 205. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
2.05
2
5.5 V 5.0 V
1.95
FRC (MHz)
4.5 V 4.0 V 3.6 V 3.3 V
1.9
1.85
2.7 V
1.8
1.75 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (C)
363
2490L-AVR-10/06
Figure 206. Calibrated 2 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. Vcc
2.05 -40 C 25 C 2 85 C
FRC (MHz)
1.95
1.9
1.85
1.8 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Figure 207. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
25 C 2.75
2.25
FRC (MHz)
1.75
1.25
0.75 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
364
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Figure 208. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
4,1 4,05 4 3,95
F RC (M Hz)
5.5 V 5.0 V
3,9 3,85 3,8 3,75 3,7 3,65 3,6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C)
4.5 V 4.0 V 3.6 V 3.3 V
2.7 V
Figure 209. Calibrated 4 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc
4.1 4.05 4 3.95
FRC (MHz )
-40 C 25 C 85 C
3.9 3.85 3.8 3.75 3.7 3.65 3.6 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
365
2490L-AVR-10/06
Figure 210. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
6.5 6 5.5 5
FRC (MHz)
25 C
4.5 4 3.5 3 2.5 2 1.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
Figure 211. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.3 8.1 7.9 7.7
FRC (MHz)
5.5 V 5.0 V 4.5 V
7.5 7.3 7.1 6.9 6.7 6.5 -40 -20 0 20 Temperature (C) 40 60 80
4.0 V 3.6 V 3.3 V
2.7 V
366
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Figure 212. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc
8.4 8.2 8
FRC (MHz)
-40 C 25 C 85 C
7.8 7.6 7.4 7.2 7 6.8 6.6 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
Figure 213. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
13 12 11 10
FRC (MHz )
25 C
9 8 7 6 5 4 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
367
2490L-AVR-10/06
Current Consumption of Peripheral Units
Figure 214. Brownout Detector Current vs. VCC
BROWNOUT DETECTOR CURRENT vs. Vcc
16 14 -40 C 12 10
Icc (uA)
25 C
8 6 4 2 0 2.5 3 3.5 4 V cc (V) 4.5 5 5.5 85 C
Figure 215. ADC Current vs. VCC (ADC CLK = 50 kHz)
ADC CURRENT vs. Vcc
ADC CLK = 50KHz 330 -40 C 310 290 270
Icc (uA)
25 C
85 C
250 230 210 190 170 150 130 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
368
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Figure 216. Aref Current vs. VCC
AREF CURRENT vs. Vcc
170 160 150 140
Icc (uA)
85 C 25 C -40 C
130 120 110 100 90 80 70 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
Figure 217. Analog Comparator Current vs. VCC
ANALOG COMPARATOR CURRENT vs. Vcc
90 85 C 80
70
Icc (uA)
25 C 60 -40 C 50
40
30 2,5 3 3,5 4 V cc (V) 4,5 5 5,5
369
2490L-AVR-10/06
Figure 218. Programming Current vs. VCC
PROGRAMMING CURRENT vs. Vcc
9 8 7 6 -40 C 25 C 85 C
Icc (mA)
5 4 3 2 1 0 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
Current Consumption in Reset and Reset Pulse width
Figure 219. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up)
RESET SUPPLY CURRENT vs. Vcc
0.1 - 1.0 MHz. EXCLUDING CURRENT THROUGH THE RESET PULLUP 3.5 3 2.5 2 1.5 1 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 5.5 V
5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V
370
ATmega64(L)
2490L-AVR-10/06
ICC (m A)
ATmega64(L)
Figure 220. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current through the Reset Pull-up)
RESET SUPPLY CURRENT vs. Vcc
1- 20MHz. EXCLUDING CURRENT THROUGH THE RESET PULLUP 40 35 30 25
Icc (mA)
5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V
20 15 10 5 0 0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
Figure 221. Minimum Reset Pulse Width vs. VCC
MINIMUM RESET PULSE WIDTH vs. Vcc
1200
1000
Pulsewidth (ns)
800
600 85 C 400 25 C -40 C 200
0 2.5 3 3.5 4 V cc (V) 4.5 5 5.5
371
2490L-AVR-10/06
Register Summary
Address
(0xFF) .. (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61)
Name
Reserved Reserved Reserved UCSR1C UDR1 UCSR1A UCSR1B UBRR1L UBRR1H Reserved Reserved UCSR0C Reserved Reserved Reserved Reserved UBRR0H Reserved ADCSRB Reserved TCCR3C TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL OCR3CH OCR3CL ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved TCCR1C OCR1CH OCR1CL Reserved Reserved Reserved TWCR TWDR TWAR TWSR TWBR OSCCAL Reserved XMCRA XMCRB Reserved EICRA Reserved SPMCSR Reserved Reserved PORTG DDRG PING PORTF DDRF
Bit 7
- - - - RXC1 RXCIE1 - - - - - - - - - - - - FOC3A COM3A1 ICNC3
Bit 6
- - - UMSEL1 TXC1 TXCIE1 - - - UMSEL0 - - - - - - - - FOC3B COM3A0 ICES3
Bit 5
- - - UPM11 UDRE1 UDRIE1 - - - UPM01 - - - - - - - - FOC3C COM3B1 -
Bit 4
- - - UPM10 FE1 RXEN1 - - - UPM00 - - - - - - - - - COM3B0 WGM33
Bit 3
- - - USBS1 DOR1 TXEN1
Bit 2
- - - UCSZ11 UPE1 UCSZ12
Bit 1
- - - UCSZ10 U2X1 RXB81
Bit 0
- - - UCPOL1 MPCM1 TXB81
Page
191 188 189 190 193 193
USART1 I/O Data Register
USART1 Baud Rate Register Low USART1 Baud Rate Register High - - USBS0 - - - - - - - - COM3C1 WGM32 - - UCSZ01 - - - - - ADTS2 - - COM3C0 CS32 - - UCSZ00 - - - - - ADTS1 - - WGM31 CS31 - - UCPOL0 - - - -
191
USART0 Baud Rate Register High - ADTS0 - - WGM30 CS30
193 248 138 133 136 138 138 139 139 139 139 139 139 140 140
Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte - - - - - FOC1A - - - - - FOC1B - - TICIE3 ICF3 - FOC1C - - OCIE3A OCF3A - - - - OCIE3B OCF3B - - - - TOIE3 TOV3 - - - - OCIE3C OCF3C - - - - OCIE1C OCF1C - -
141 142 137 139 139
Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte - - - TWINT TWA6 TWS7 - - - TWEA TWA5 TWS6 - - - TWSTA TWA4 TWS5 - - - TWSTO TWA3 TWS4 - - - TWWC TWA2 TWS3 - - - TWEN TWA1 - - - - - TWA0 TWPS1 - - - TWIE TWGCE TWPS0
206 208 208 207 206 43
Two-wire Serial Interface Data Register
Two-wire Serial Interface Bit Rate Register Oscillator Calibration Register - - XMBK - ISC31 - SPMIE - - - - - PORTF7 DDF7 - SRL2 - - ISC30 - RWWSB - - - - - PORTF6 DDF6 - SRL1 - - ISC21 - - - - - - - PORTF5 DDF5 - SRL0 - - ISC20 - RWWSRE - - PORTG4 DDG4 PING4 PORTF4 DDF4 - SRW01 - - ISC11 - BLBSET - - PORTG3 DDG3 PING3 PORTF3 DDF3 - SRW00 XMM2 - ISC10 - PGWRT - - PORTG2 DDG2 PING2 PORTF2 DDF2 - SRW11 XMM1 - ISC01 - PGERS - - PORTG1 DDG1 PING1 PORTF1 DDF1 XMM0 - ISC00 - SPMEN - - PORTG0 DDG0 PING0 PORTF0 DDF0 -
32 34 90 282
89 89 89 88 89
372
ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Register Summary (Continued)
Address
(0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21)
Name
Reserved SREG SPH SPL XDIV Reserved EICRB EIMSK EIFR TIMSK TIFR MCUCR MCUCSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 OCDR WDTCR SFIOR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR ADMUX ADCSRA ADCH ADCL PORTE DDRE PINE
Bit 7
- I SP15 SP7 XDIVEN - ISC71 INT7 INTF7 OCIE2 OCF2 SRE JTD FOC0
Bit 6
- T SP14 SP6 XDIV6 - ISC70 INT6 INTF6 TOIE2 TOV2 SRW10 - WGM00
Bit 5
- H SP13 SP5 XDIV5 - ISC61 INT5 INTF5 TICIE1 ICF1 SE - COM01
Bit 4
- S SP12 SP4 XDIV4 - ISC60 INT4 INTF4 OCIE1A OCF1A SM1 JTRF COM00
Bit 3
- V SP11 SP3 XDIV3 - ISC51 INT3 INTF3 OCIE1B OCF1B SM0 WDRF WGM01
Bit 2
- N SP10 SP2 XDIV2 - ISC50 INT2 INTF TOIE1 TOV1 SM2 BORF CS02
Bit 1
- Z SP9 SP1 XDIV1 - ISC41 INT1 INTF1 OCIE0 OCF0 IVSEL EXTRF CS01
Bit 0
- C SP8 SP0 XDIV0 - ISC40 INT0 INTF0 TOIE0 TOV0 IVCE PORF CS00
Page
12 14 14 39 91 92 92 109, 140, 160 109, 142, 160 32, 46, 64 55, 257 104 106 106
Timer/Counter0 (8 Bit) Timer/Counter0 Output Compare Register - COM1A1 ICNC1 - COM1A0 ICES1 - COM1B1 - - COM1B0 WGM13 AS0 COM1C1 WGM12 TCN0UB COM1C0 CS12 OCR0UB WGM11 CS11 TCR0UB WGM10 CS10
107 133 136 138 138 139 139 139 139 140 140
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bit) Timer/Counter2 Output Compare Register IDRD/ OCDR7 - TSM - OCDR6 - - - OCDR5 - - - OCDR4 WDCE - - OCDR3 WDE ACME - OCDR2 WDP2 PUD OCDR1 WDP1 PSR0 OCDR0 WDP0 PSR321
157 159 160 254 57 72, 111, 145, 228 22 22 22
EEPROM Address Register High Byte
EEPROM Address Register Low Byte EEPROM Data Register - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 ACD REFS1 ADEN - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC0 TXCIE0 ACBG REFS0 ADSC - PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - DORD UDRE0 UDRIE0 ACO ADLAR ADATE - PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 - MSTR FE0 RXEN0 ACI MUX4 ADIF EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 - CPOL DOR0 TXEN0 ACIE MUX3 ADIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 - CPHA UPE0 UCSZ02 ACIC MUX2 ADPS2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 - SPR1 U2X0 RXB80 ACIS1 MUX1 ADPS1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM0 TXB80 ACIS0 MUX0 ADPS0
22 87 87 87 87 87 87 87 87 88 88 88 88 169 169 167 188 189 190 193 229 244 246 247 247
SPI Data Register
USART0 I/O Data Register
USART0 Baud Rate Register Low
ADC Data Register High Byte ADC Data Register Low byte PORTE7 DDE7 PINE7 PORTE6 DDE6 PINE6 PORTE5 DDE5 PINE5 PORTE4 DDE4 PINE4 PORTE3 DDE3 PINE3 PORTE2 DDE2 PINE2 PORTE1 DDE1 PINE1 PORTE0 DDE0 PINE0
88 88 88
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Register Summary (Continued)
Address
0x00 (0x20)
Name
PINF
Bit 7
PINF7
Bit 6
PINF6
Bit 5
PINF5
Bit 4
PINF4
Bit 3
PINF3
Bit 2
PINF2
Bit 1
PINF1
Bit 0
PINF0
Page
89
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
374
ATmega64(L)
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ATmega64(L)
Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k
Description
Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared
Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
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Instruction Set Summary (Continued)
BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Z Rd, Z+ k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA TRANSFER INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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ATmega64(L)
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ATmega64(L)
Instruction Set Summary (Continued)
CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None None 1 1 1 N/A Clear Half Carry Flag in SREG H0 H 1
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Ordering Information
Speed (MHz) Power Supply Ordering Code ATmega64L-8AC ATmega64L-8MC 8 2.7 - 5.5 ATmega64L-8AI ATmega64L-8MI ATmega64L-8AU(2) ATmega64L-8MU(2) ATmega64-16AC ATmega64-16MC 16 4.5 - 5.5 ATmega64-16AI ATmega64-16MI ATmega64-16AU(2) ATmega64-16MU(2) Package(1) 64A 64M1 64A 64M1 64A 64M1 64A 64M1 64A 64M1 64A 64M1 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 64A 64M1 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
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Packaging Information
64A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 64A REV. B
R
379
2490L-AVR-10/06
64M1
D
Marked Pin# 1 ID
E
C
TOP VIEW
SEATING PLANE
A1 A
K L D2
Pin #1 Corner
0.08 C
SIDE VIEW
1 2 3
Option A
Pin #1 Triangle
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
Option B
Pin #1 Chamfer (C 0.30)
E2
MIN 0.80 - 0.18 8.90 5.20 8.90 5.20
NOM 0.90 0.02 0.25 9.00 5.40 9.00 5.40 0.50 BSC
MAX 1.00 0.05 0.30 9.10 5.60 9.10 5.60
NOTE
A A1 b D
K b e
Option C
D2
Pin #1 Notch (0.20 R)
E E2 e L
BOTTOM VIEW
0.35 1.25
0.40 1.40
0.45 1.55
Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994.
K
5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. G
R
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ATmega64(L)
Errata
ATmega64, rev. A to C
The revision letter in this section refers to the revision of the ATmega64 device. * * * * *
First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register IDCODE masks data from TDI input
1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. Stabilizing time needed when changing XDIV Register After increasing the source clock frequency more than 2% with settings in the XDIV register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The NOP instruction will always be executed correctly also right after a frequency change. Thus, the next 8 instructions after the change should be NOP instructions. To ensure this, follow this procedure: 1.Clear the I bit in the SREG Register. 2.Set the new pre-scaling factor in XDIV register. 3.Execute 8 NOP instructions 4.Set the I bit in SREG This will ensure that all subsequent instructions will execute correctly. Assembly Code Example:
CLI OUT NOP NOP NOP NOP NOP NOP NOP NOP SEI XDIV, temp ; clear global interrupt enable ; set new prescale value ; no operation ; no operation ; no operation ; no operation ; no operation ; no operation ; no operation ; no operation ; clear global interrupt enable
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4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior follows errata number 1., and the same Fix / Workaround is applicable on this errata. 5. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - - If ATmega64 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega64 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega64 while reading the Device ID Registers of preceding devices of the boundary scan chain. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega64 must be the fist device in the chain.
-
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Datasheet Revision History
Changes from Rev. 2490K-04/06 to Rev. 2490L-10/06
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 1. Added note to "Timer/Counter Oscillator" on page 45. 2. Updated "Fast PWM Mode" on page 125. 3. Updated Table 52 on page 104, Table 54 on page 105, Table 59 on page 134, Table 61 on page 136, Table 64 on page 158, and Table 66 on page 158. 4. Updated "Errata" on page 381.
Changes from Rev. 2490J-03/05 to Rev. 2490K-04/06
1. Updated Figure 2 on page 3. 2. Added "Resources" on page 8. 3. Added Addresses in Register Descriptions. 4. Updated "SPI - Serial Peripheral Interface" on page 163. 5. Updated Register- and bit names in "USART" on page 171. 6. Updated note in "Bit Rate Generator Unit" on page 204. 7. Updated Features in "Analog to Digital Converter" on page 231.
Changes from Rev. 2490I-10/04 to Rev. 2490J-03/05
1. MLF-package alternative changed to "Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF". 2. Updated "Electrical Characteristics" on page 327 3. Updated "Ordering Information" on page 378
Changes from Rev. 2490H-10/04 to Rev. 2490I-11/04
1. Removed "Preliminary" and TBD's. 2. Updated Table 8 on page 40, Table 11 on page 42, Table 19 on page 52, Table 132 on page 329, Table 134 on page 332. 3. Updated features in "Analog to Digital Converter" on page 231. 4. Updated "Electrical Characteristics" on page 327.
Changes from Rev. 2490G-03/04 to Rev. 2490H-10/04
1. Removed references to Analog Ground, IC1/IC3 changed to ICP1/ICP3, Input Capture Trigger changed to Input Capture Pin. 2. Updated "ATmega103 and ATmega64 Compatibility" on page 4. 3. Updated "External Memory Interface" on page 27 4. Updated "XDIV - XTAL Divide Control Register" to "Clock Sources" on page 38.
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5. Updated code example in "WDTCR - Watchdog Timer Control Register" on page 57. 6. Added section "Unconnected Pins" on page 71. 7. Updated Table 19 on page 52, Table 20 on page 56, Table 95 on page 237, and Table 60 on page 135. 8. Updated Figure 116 on page 240. 9. Updated "Version" on page 256. 10. Updated "DC Characteristics" on page 327. 11. Updated "Typical Characteristics" on page 342. 12. Updated features in"Analog to Digital Converter" on page 231 and Table 136 on page 335. 13. Updated "Ordering Information" on page 378.
Changes from Rev. 2490F-12/03 to Rev. 2490G-03/04 Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03
1. Updated "Errata" on page 381.
1. Updated "Calibrated Internal RC Oscillator" on page 43.
1. Updated note in "XDIV - XTAL Divide Control Register" on page 39. 2. Updated "JTAG Interface and On-chip Debug System" on page 50. 3. Updated "TAP - Test Access Port" on page 249 regarding JTAGEN. 4. Updated description for the JTD bit on page 259. 5. Added a note regarding JTAGEN fuse to Table 118 on page 293. 6. Updated RPU values in "DC Characteristics" on page 327. 7. Updated "ADC Characteristics" on page 334. 8. Added a proposal for solving problems regarding the JTAG instruction IDCODE in "Errata" on page 381.
Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03
1. Added reference to Table 124 on page 297 from both SPI Serial Programming and Self Programming to inform about the Flash page size. 2. Added Chip Erase as a first step under "Programming the Flash" on page 324 and "Programming the EEPROM" on page 325.
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3. Corrected OCn waveforms in Figure 52 on page 126. 4. Various minor Timer1 corrections. 5. Improved the description in "Phase Correct PWM Mode" on page 101 and on page 154. 6. Various minor TWI corrections. 7. Added note under "Filling the Temporary Buffer (Page Loading)" about writing to the EEPROM during an SPM page load. 8. Removed ADHSM completely. 9. Added note about masking out unused bits when reading the Program Counter in "Stack Pointer" on page 14. 10. Added section "EEPROM Write During Power-down Sleep Mode" on page 25. 11. Changed VHYST value to 120 in Table 19 on page 52. 12. Added information about conversion time for Differential mode with Auto Triggering on page 235. 13. Added tWD_FUSE in Table 128 on page 310. 14. Updated "Packaging Information" on page 379.
Changes from Rev. 2490B-09/02 to Rev. 2490C-09/02 Changes from Rev. 2490A-10/01 to Rev. 2490B-09/02
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
1. Added 64-pad QFN/MLF Package and updated "Ordering Information" on page 378. 2. Added the section "Using all Locations of External Memory Smaller than 64 KB" on page 35. 3. Added the section "Default Clock Source" on page 39. 4. Renamed SPMCR to SPMCSR in entire document. 5. Added Some Preliminary Test Limits and Characterization Data Removed some of the TBD's and corrected data in the following tables and pages: Table 2 on page 24, Table 7 on page 38, Table 9 on page 41, Table 10 on page 41, Table 12 on page 42, Table 14 on page 43, Table 16 on page 44, Table 19 on page 52, Table 20 on page 56, Table 22 on page 58, "DC Characteristics" on page 327, Table 131 on page 329, Table 134 on page 332, Table 136 on page 335, and Table 137 - Table 144. 6. Removed Alternative Algortihm for Leaving JTAG Programming Mode. See "Leaving Programming Mode" on page 323.
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7. Improved description on how to do a polarity check of the ADC diff results in "ADC Conversion Result" on page 243. 8. Updated Programming Figures: Figure 138 on page 295 and Figure 147 on page 308 are updated to also reflect that AVCC must be connected during Programming mode. Figure 142 on page 304 added to illustrate how to program the fuses. 9. Added a note regarding usage of the "PROG_PAGELOAD (0x6)" and "PROG_PAGEREAD (0x7)" instructions on page 315. 10. Updated "TWI - Two-wire Serial Interface" on page 198. More details regarding use of the TWI Power-down operation and using the TWI as master with low TWBRR values are added into the data sheet. Added the note at the end of the "Bit Rate Generator Unit" on page 204. Added the description at the end of "Address Match Unit" on page 205. 11. Updated Description of OSCCAL Calibration Byte. In the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of "OSCCAL - Oscillator Calibration Register(1)" on page 43 and "Calibration Byte" on page 294. 12. When using external clock there are some limitations regards to change of frequency. This is descried in "External Clock" on page 44 and Table 131 on page 329. 13. Added a sub section regarding OCD-system and power consumption in the section "Minimizing Power Consumption" on page 49. 14. Corrected typo (WGM-bit setting) for: - - - - "Fast PWM Mode" on page 99 (Timer/Counter0). "Phase Correct PWM Mode" on page 101 (Timer/Counter0). "Fast PWM Mode" on page 152 (Timer/Counter2). "Phase Correct PWM Mode" on page 154 (Timer/Counter2).
15. Corrected Table 81 on page 192 (USART). 16. Corrected Table 102 on page 263 (Boundary-Scan)
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Table of Contents
Features................................................................................................ 1 Pin Configuration................................................................................. 2
Disclaimer ............................................................................................................. 2
Overview............................................................................................... 3
Block Diagram ...................................................................................................... 3 ATmega103 and ATmega64 Compatibility ........................................................... 4 Pin Descriptions.................................................................................................... 5
Resources ............................................................................................ 8 About Code Examples......................................................................... 9 AVR CPU Core ................................................................................... 10
Introduction ......................................................................................................... Architectural Overview........................................................................................ ALU - Arithmetic Logic Unit................................................................................ Status Register ................................................................................................... General Purpose Register File ........................................................................... Stack Pointer ...................................................................................................... Instruction Execution Timing............................................................................... Reset and Interrupt Handling.............................................................................. 10 10 11 12 13 14 15 15
AVR Memories ................................................................................... 18
In-System Reprogrammable Flash Program Memory ........................................ SRAM Data Memory........................................................................................... EEPROM Data Memory...................................................................................... I/O Memory ......................................................................................................... External Memory Interface.................................................................................. XMEM Register Description................................................................................ 18 19 21 26 27 32
System Clock and Clock Options .................................................... 37
Clock Systems and their Distribution .................................................................. Clock Sources..................................................................................................... Default Clock Source .......................................................................................... Crystal Oscillator................................................................................................. Low-frequency Crystal Oscillator ........................................................................ External RC Oscillator ........................................................................................ Calibrated Internal RC Oscillator ........................................................................ External Clock..................................................................................................... Timer/Counter Oscillator..................................................................................... 37 38 39 39 41 42 43 44 45
Power Management and Sleep Modes............................................. 46
Idle Mode ............................................................................................................ 47 ADC Noise Reduction Mode............................................................................... 47
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2490L-AVR-10/06
Power-down Mode.............................................................................................. Power-save Mode............................................................................................... Standby Mode..................................................................................................... Extended Standby Mode .................................................................................... Minimizing Power Consumption .........................................................................
47 47 48 48 49
System Control and Reset ................................................................ 51
Internal Voltage Reference ................................................................................. 56 Watchdog Timer ................................................................................................. 56 Timed Sequences for Changing the Configuration of the Watchdog Timer ....... 60
Interrupts ............................................................................................ 61
Interrupt Vectors in ATmega64........................................................................... 61
I/O Ports.............................................................................................. 66
Introduction ......................................................................................................... Ports as General Digital I/O ................................................................................ Alternate Port Functions ..................................................................................... Register Description for I/O Ports ....................................................................... 66 67 71 87
External Interrupts............................................................................. 90 8-bit Timer/Counter0 with PWM and Asynchronous Operation .... 93
Overview............................................................................................................. 93 Timer/Counter Clock Sources............................................................................. 94 Counter Unit........................................................................................................ 95 Output Compare Unit.......................................................................................... 95 Compare Match Output Unit ............................................................................... 97 Modes of Operation ............................................................................................ 98 Timer/Counter Timing Diagrams....................................................................... 102 8-bit Timer/Counter Register Description ......................................................... 104 Asynchronous Operation of the Timer/Counter ................................................ 107 Timer/Counter Prescaler................................................................................... 110
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)....... 112
Overview........................................................................................................... Accessing 16-bit Registers ............................................................................... Timer/Counter Clock Sources........................................................................... Counter Unit...................................................................................................... Input Capture Unit............................................................................................. Output Compare Units ...................................................................................... Compare Match Output Unit ............................................................................. Modes of Operation .......................................................................................... Timer/Counter Timing Diagrams....................................................................... 16-bit Timer/Counter Register Description ....................................................... 112 115 117 117 119 121 122 124 131 133
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ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers .... 144 8-bit Timer/Counter2 with PWM...................................................... 146
Overview........................................................................................................... Timer/Counter Clock Sources........................................................................... Counter Unit...................................................................................................... Output Compare Unit........................................................................................ Compare Match Output Unit ............................................................................. Modes of Operation .......................................................................................... Timer/Counter Timing Diagrams....................................................................... 8-bit Timer/Counter Register Description ......................................................... 146 147 148 148 150 151 155 157
Output Compare Modulator (OCM1C2).......................................... 161
Overview........................................................................................................... 161 Description........................................................................................................ 161
SPI - Serial Peripheral Interface..................................................... 163
SS Pin Functionality.......................................................................................... 167 Data Modes ...................................................................................................... 170
USART .............................................................................................. 171
Overview........................................................................................................... Clock Generation .............................................................................................. Frame Formats ................................................................................................. USART Initialization.......................................................................................... Data Transmission - The USART Transmitter ................................................. Data Reception - The USART Receiver .......................................................... Asynchronous Data Reception ......................................................................... Multi-processor Communication Mode ............................................................. USART Register Description ............................................................................ Examples of Baud Rate Setting........................................................................ 171 172 175 176 177 181 184 187 188 193
TWI - Two-wire Serial Interface...................................................... 198
Features............................................................................................................ Two-wire Serial Interface Bus Definition........................................................... Data Transfer and Frame Format ..................................................................... Multi-master Bus Systems, Arbitration and Synchronization ............................ Overview of the TWI Module ............................................................................ TWI Register Description.................................................................................. Using the TWI ................................................................................................... Transmission Modes......................................................................................... Multi-master Systems and Arbitration............................................................... 198 198 199 202 204 206 209 213 226
Analog Comparator ......................................................................... 228
Analog Comparator Multiplexed Input .............................................................. 230
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2490L-AVR-10/06
Analog to Digital Converter ............................................................ 231
Features............................................................................................................ Operation .......................................................................................................... Starting a Conversion ....................................................................................... Prescaling and Conversion Timing ................................................................... Changing Channel or Reference Selection ...................................................... ADC Noise Canceler......................................................................................... ADC Conversion Result.................................................................................... 231 232 233 234 237 239 243
JTAG Interface and On-chip Debug System ................................. 249
Features............................................................................................................ Overview........................................................................................................... TAP - Test Access Port.................................................................................... TAP Controller .................................................................................................. Using the Boundary -scan Chain ...................................................................... Using the On-chip Debug system ..................................................................... On-chip Debug Specific JTAG Instructions ...................................................... On-chip Debug Related Register in I/O Memory .............................................. Using the JTAG Programming Capabilities ...................................................... Bibliography ...................................................................................................... 249 249 249 251 252 252 253 254 254 254
IEEE 1149.1 (JTAG) Boundary-scan .............................................. 255
Features............................................................................................................ System Overview.............................................................................................. Data Registers .................................................................................................. Boundary-scan Specific JTAG Instructions ...................................................... Boundary-scan Related Register in I/O Memory .............................................. Boundary-scan Chain ....................................................................................... ATmega64 Boundary-scan Order..................................................................... Boundary-scan Description Language Files ..................................................... 255 255 255 257 259 259 271 277
Boot Loader Support - Read-While-Write Self-programming ..... 278
Features............................................................................................................ Application and Boot Loader Flash Sections .................................................... Read-While-Write and No Read-While-Write Flash Sections........................... Boot Loader Lock Bits....................................................................................... Entering the Boot Loader Program ................................................................... Addressing the Flash During Self-programming............................................... Self-programming the Flash ............................................................................. 278 278 278 280 282 284 285
Memory Programming..................................................................... 291
Program and Data Memory Lock Bits............................................................... Fuse Bits........................................................................................................... Signature Bytes ................................................................................................ Calibration Byte ................................................................................................ Parallel Programming Parameters, Pin Mapping, and Commands .................. 291 292 294 294 294
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ATmega64(L)
2490L-AVR-10/06
ATmega64(L)
Parallel Programming ....................................................................................... Serial Downloading........................................................................................... SPI Serial Programming Pin Mapping .............................................................. Programming Via the JTAG Interface............................................................... 298 307 308 313
Electrical Characteristics................................................................ 327
Absolute Maximum Ratings*............................................................................. DC Characteristics............................................................................................ External Clock Drive Waveforms ...................................................................... External Clock Drive ......................................................................................... Two-wire Serial Interface Characteristics ......................................................... SPI Timing Characteristics ............................................................................... ADC Characteristics ......................................................................................... External Data Memory Timing .......................................................................... 327 327 329 329 330 332 334 337
Typical Characteristics ................................................................... 342 Register Summary ........................................................................... 372 Instruction Set Summary ................................................................ 375 Ordering Information....................................................................... 378 Packaging Information .................................................................... 379
64A ................................................................................................................... 379 64M1................................................................................................................. 380
Errata ................................................................................................ 381
ATmega64, rev. A to C ..................................................................................... 381
Datasheet Revision History ............................................................ 383
Changes from Rev. 2490K-04/06 to Rev. 2490L-10/06.................................... Changes from Rev. 2490J-03/05 to Rev. 2490K-04/06.................................... Changes from Rev. 2490I-10/04 to Rev. 2490J-03/05 ..................................... Changes from Rev. 2490H-10/04 to Rev. 2490I-11/04 .................................... Changes from Rev. 2490G-03/04 to Rev. 2490H-10/04................................... Changes from Rev. 2490F-12/03 to Rev. 2490G-03/04 ................................... Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 ................................... Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03 ................................... Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03................................... Changes from Rev. 2490B-09/02 to Rev. 2490C-09/02 ................................... Changes from Rev. 2490A-10/01 to Rev. 2490B-09/02 ................................... 383 383 383 383 383 384 384 384 384 385 385
Table of Contents ................................................................................. i
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